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41. 发明授权

US5598424A Error detection structure and method for serial or parallel data stream using partial polynomial check 失效
标题翻译：使用部分多项式检查的串行或并行数据流的错误检测结构和方法
公开(公告)号：US5598424A
公开(公告)日：1997-01-28
申请号：US259765
申请日：1994-06-14
申请人： Charles R. Erickson , Philip M. Freidin , William A. Wilkie
发明人： Charles R. Erickson , Philip M. Freidin , William A. Wilkie
IPC分类号： G06F11/10 , H03M13/00 , H03M13/09 , H04L1/00 , G06F11/00
CPC分类号： H03M13/091 , G06F11/10
摘要： The present invention provides a means and method of generating a long error checking polynomial remainder having the ability to detect errors with high reliability and inserting only a subset of the polynomial remainder periodically into a data stream, then at the receiving end recalculating the polynomial remainder and checking the inserted subset for errors. The polynomial has the property that the current remainder value is a function of all data previously transmitted in a transmission session. The subset transmitted also preferably has this property. A longer subset of the polynomial remainder, or the full polynomial remainder, may be inserted less frequently, and is preferably sent and tested at the end of the transmission session. Both serial and parallel data streams may be checked.
摘要翻译：本发明提供一种生成具有高可靠性检测误差的能力的长错误检验多项式余数的装置和方法，并且仅将多项式余数的子集周期性地插入到数据流中，然后在接收端重新计算多项式余数和检查插入的子集是否有错误。多项式具有当前余数值是传输会话中先前传输的所有数据的函数的性质。传输的子集也优选具有该属性。可以较少频繁地插入多项式余数的较长子集或全多项式余数，并且优选地在传输会话结束时发送和测试。可以检查串行和并行数据流。

42. 发明授权

US5523963A Logic structure and circuit for fast carry 失效
标题翻译：逻辑结构和电路快速携带
公开(公告)号：US5523963A
公开(公告)日：1996-06-04
申请号：US479896
申请日：1995-06-07
申请人： Hung-Cheng Hsieh, deceased , by William S. Carter, administrator , Charles R. Erickson , Edmond Y. Cheung
发明人： Hung-Cheng Hsieh, deceased , by William S. Carter, administrator , Charles R. Erickson , Edmond Y. Cheung
IPC分类号： G06F7/50 , G06F7/57
CPC分类号： G06F7/57 , G06F7/503 , G06F7/5057 , G06F7/506
摘要： Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal.
摘要翻译：使用包括组合函数发生器和存储元件的多个块并且通过可编程互连结构互连的可编程逻辑器件，用于执行使用用于产生进位功能的逻辑的算术功能。当要处理大量的位时，进位功能通常会导致显着的延迟或需要大量附加组件以高速获得结果。本发明提供逻辑块内的专用硬件，用于快速执行进位功能并具有最少数量的部件。本发明利用以下事实：当要添加的两个二进制比特不相等时，要添加到两个比特的进位信号可以被传播到下一个更高有效比特，并且该比特中的一个可以用作进位信号，当这些位是相等的。

43. 发明授权

US5321704A Error detection structure and method using partial polynomial check 失效
标题翻译：误差检测结构和方法采用部分多项式检验
公开(公告)号：US5321704A
公开(公告)日：1994-06-14
申请号：US641994
申请日：1991-01-16
申请人： Charles R. Erickson , Philip M. Freidin
发明人： Charles R. Erickson , Philip M. Freidin
IPC分类号： G06F11/10 , H03M13/00 , H03M13/09 , H04L1/00
CPC分类号： H03M13/091 , G06F11/10
摘要： The present invention provides a means and method of generating a long error checking polynomial remainder having the ability to detect errors with high reliability and inserting only a subset of the polynomial remainder periodically into a data stream, then at the receiving end recalculating the polynomial remainder and checking the inserted subset for errors. The polynomial has the property that the current remainder value is a function of all data previously transmitted in a transmission session. The subset transmitted also preferably has this property. A longer subset of the polynomial remainder, or the full polynomial remainder, may be inserted less frequently, and is preferably sent and tested at the end of the transmission session.
摘要翻译：本发明提供一种生成具有高可靠性检测误差的能力的长错误检验多项式余数的装置和方法，并且仅将多项式余数的子集周期性地插入到数据流中，然后在接收端重新计算多项式余数和检查插入的子集是否有错误。多项式具有当前余数值是传输会话中先前传输的所有数据的函数的性质。传输的子集也优选具有该属性。可以较少频繁地插入多项式余数的较长子集或全多项式余数，并且优选地在传输会话结束时发送和测试。

44. 发明授权

US5140193A Programmable connector for programmable logic device 失效
标题翻译：可编程逻辑器件的可编程连接器
公开(公告)号：US5140193A
公开(公告)日：1992-08-18
申请号：US499759
申请日：1990-03-27
申请人： Ross H. Freeman, deceased , Khue Duong , Hung-Cheng Hsieh , Charles R. Erickson , William S. Carter
发明人： Ross H. Freeman, deceased , Khue Duong , Hung-Cheng Hsieh , Charles R. Erickson , William S. Carter
IPC分类号： G06F3/00 , H01L21/82 , H03K19/173
CPC分类号： H03K19/1736
摘要： A structure especially useful in a configurable logic array includes a plurality of conductive interconnect lines located along the perimeter of a logic array chip. Lines running from exterior pins or pads can be used by a programmable interconnect circuit to control signals applied to these interconnect lines. In particular, both the signal and the complement of the signal can be used by the programmable interconnect to control application of a supply voltage to an interconnect line. A second supply voltage is applied through a resistor to the interconnect line with the result that the interconnect line will carry a logical signal representing a logical function, for example AND, of a selected set of input signals or their complements. Lines running from points interior to the configurable logic array chip may also contribute to the signal generated on an interconnect line. In one embodiment, bidirectional programmable interconnect circuits allow the input pins to function as either input or output pins. An application of the decoder circuit is described for use with a latch as a data/address demultiplexer.

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