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41. 发明授权

US07157646B2 Circuitized substrate with split conductive layer, method of making same, electrical assembly utilizing same, and information handling system utilizing same 失效
标题翻译：具有分裂导电层的电路化基板，其制造方法，利用其组合的电气组件以及利用其的信息处理系统
公开(公告)号：US07157646B2
公开(公告)日：2007-01-02
申请号：US10882167
申请日：2004-07-02
申请人： John M. Lauffer , James M. Larnerd , Voya R. Markovich
发明人： John M. Lauffer , James M. Larnerd , Voya R. Markovich
IPC分类号： H05K1/11
CPC分类号： H01L23/49811 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H05K1/0216 , H05K1/0256 , H05K1/056 , H05K3/0047 , H05K3/429 , H05K3/44 , H05K3/4641 , H05K2201/093 , H05K2201/09345 , H05K2201/09481 , H05K2201/09663 , H05K2201/0969 , H05K2203/0323 , H05K2203/1476 , Y10T29/49126 , Y10T29/49155 , Y10T29/49162 , Y10T29/49165 , Y10T29/49176 , H01L2224/0401
摘要： A circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within a product (e.g., electrical assembly) which includes the substrate as part thereof. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e.g., a mainframe computer, are also provided.
摘要翻译：电路化基板，其包括多个邻接的开放段，其在导电层内限定面对的边缘部分，以隔离导电层的分离部分，使得该层可用于不同的功能，例如功率和接地元件内部的功能和接地元件包括基板作为其一部分的产品（例如，电气组件）。还提供了制造衬底的方法，利用衬底的电组件，还利用衬底的多层电路化组件和诸如主机的信息处理系统。

42. 发明授权

US07152319B2 Method of making high speed circuit board 失效
标题翻译：制造高速电路板的方法
公开(公告)号：US07152319B2
公开(公告)日：2006-12-26
申请号：US10811817
申请日：2004-03-30
申请人： Benson Chan , John M. Lauffer , How T. Lin , Voya R. Markovich , David L. Thomas
发明人： Benson Chan , John M. Lauffer , How T. Lin , Voya R. Markovich , David L. Thomas
IPC分类号： H01K3/10
CPC分类号： H05K3/4688 , H01L23/3128 , H01L23/5383 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2224/16 , H01L2224/73253 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H01L2924/3025 , H05K1/024 , H05K1/113 , H05K3/4623 , H05K2201/09536 , H05K2201/096 , H05K2203/061 , Y10T29/49126 , Y10T29/49165 , H01L2224/0401
摘要： A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.
摘要翻译：包括两个多层部分的多层PCB，其中之一能够电连接安装在PCB上的电子部件，以确保其间的高频连接。 PCB还包括常规PCB部分以降低成本，同时确保具有令人满意的整体厚度的结构以用于PCB领域。这些组件的内部部分也可以进行耦合。也提供了制造这些结构的方法。

43. 发明授权

US07076869B2 Solid via layer to layer interconnect 失效
标题翻译：实体通过层间互连
公开(公告)号：US07076869B2
公开(公告)日：2006-07-18
申请号：US10260153
申请日：2002-09-27
申请人： Brian E. Curcio , Donald S. Farquhar , Voya R. Markovich , Konstantinos I. Papathomas
发明人： Brian E. Curcio , Donald S. Farquhar , Voya R. Markovich , Konstantinos I. Papathomas
IPC分类号： H01K3/10
CPC分类号： H05K3/462 , H05K3/321 , H05K3/423 , H05K3/4623 , H05K2201/09536 , H05K2201/09563 , H05K2201/096 , H05K2203/0733 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： The present invention relates to a method for providing an interconnect between layers of a multilayer circuit board. A first via extending through a total thickness of a first layer is formed. The first via is totally filled with a first solid conductive plug and an end of the first solid conductive plug includes a first contact pad that is in contact with a surface of the first layer. A second via extending through a total thickness of a second layer is formed. The second via totally filling with a second solid conductive plug and an end of the second solid conductive plug includes a second contact pad that is in contact with a surface of the second layer. The second layer is electrically and mechanically coupled to the first layer by an electrically conductive adhesive that is in electrical and mechanical contact with both the end of the first plug and the end of the second plug.
摘要翻译：本发明涉及一种在多层电路板的层之间提供互连的方法。形成延伸通过第一层的总厚度的第一通孔。第一通孔完全填充有第一固体导电插塞，并且第一固体导电插塞的端部包括与第一层的表面接触的第一接触垫。形成延伸穿过第二层的总厚度的第二通孔。通过完全填充第二固体导电插塞和第二固体导电插塞的端部的第二通孔包括与第二层的表面接触的第二接触垫。第二层通过与第一插头的端部和第二插头的端部电接触和机械接触的导电粘合剂电和机械地耦合到第一层。

44. 发明授权

US06894228B2 High performance dense wire for printed circuit board 失效
标题翻译：高性能致密线用于印刷电路板
公开(公告)号：US06894228B2
公开(公告)日：2005-05-17
申请号：US10217674
申请日：2002-08-12
申请人： Donald O. Anstrom , Bruce J. Chamberlin , John M. Lauffer , Voya R. Markovich , David L. Thomas
发明人： Donald O. Anstrom , Bruce J. Chamberlin , John M. Lauffer , Voya R. Markovich , David L. Thomas
IPC分类号： H01L23/538 , H05K1/02 , H05K3/46
CPC分类号： H01L23/5383 , H01L2924/0002 , H01L2924/3011 , H05K1/0263 , H05K1/0265 , H05K3/4602 , H05K3/4611 , H05K2201/0352 , H05K2201/09536 , H05K2201/096 , H05K2203/061 , H05K2203/1581 , H01L2924/00
摘要： A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably “short” wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.
摘要翻译：一种在印刷电路板或芯片载体应用中实现密集布线的方法和结构，其提供优异的电特性，同时保持系统电阻和特征阻抗要求。密集布线的特征在于要求所有导线具有足够的横截面积，以确保所使用的最长的导线不会通过分选导线长度而不超过最大电阻，并允许可接受的“短”导线使用更密集的电路线或提供短路必要时的短路线路长度，尽可能切换到较不密集，较低电阻的线路。本公开还提供了组件区域中的密集布线，然后可以通过应用埋入通孔将其转换成低电阻布线。

45. 发明授权

US06809269B2 Circuitized substrate assembly and method of making same 有权
公开(公告)号：US06809269B2
公开(公告)日：2004-10-26
申请号：US10322527
申请日：2002-12-19
申请人： James W. Fuller, Jr. , John M. Lauffer , Voya R. Markovich
发明人： James W. Fuller, Jr. , John M. Lauffer , Voya R. Markovich
IPC分类号： H01R1204
CPC分类号： H05K3/462 , H05K3/321 , H05K3/4069 , H05K3/429 , H05K3/4623 , H05K2201/0347 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49151 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167
摘要： A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

46. 发明授权

US06781064B1 Printed circuit boards for electronic device packages having glass free non-conductive layers and method of forming same 失效
标题翻译：具有无玻璃非导电层的电子器件封装的印刷电路板及其形成方法
公开(公告)号：US06781064B1
公开(公告)日：2004-08-24
申请号：US09342584
申请日：1999-06-29
申请人： Bernd K. Appelt , Anilkumar C. Bhatt , James W. Fuller, Jr. , John M. Lauffer , Voya R. Markovich , William J. Rudik , William E. Wilson
发明人： Bernd K. Appelt , Anilkumar C. Bhatt , James W. Fuller, Jr. , John M. Lauffer , Voya R. Markovich , William J. Rudik , William E. Wilson
IPC分类号： H05K103
CPC分类号： H01L23/564 , H01L21/481 , H01L23/498 , H01L23/49894 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H05K1/036 , H05K1/0366 , H05K3/429 , H05K3/4626 , H05K3/4641 , H05K2201/0195 , H05K2201/0769 , H05K2201/09718 , H05K2201/09881 , H01L2924/00014 , H01L2924/00012
摘要： A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package. This printed circuit board includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.
摘要翻译：一种用于诸如球栅阵列封装或有机芯片载体封装的电子器件封装中的印刷电路板。该印刷电路板包括一个无玻璃的电介质，用于分离和绝缘电源芯，电路或电镀通孔，以防止导电材料沿玻璃基预浸料衬底迁移引起的短路。

47. 发明授权

US06753612B2 Economical high density chip carrier 有权
标题翻译：经济高密度芯片载体
公开(公告)号：US06753612B2
公开(公告)日：2004-06-22
申请号：US09827014
申请日：2001-04-05
申请人： Sylvia Adae-Amoakoh , John S. Kresge , Voya R. Markovich , Thurston B. Youngs, Jr.
发明人： Sylvia Adae-Amoakoh , John S. Kresge , Voya R. Markovich , Thurston B. Youngs, Jr.
IPC分类号： H01L2940
CPC分类号： H05K3/4069 , H01L21/4857 , H01L21/486 , H01L23/49822 , H01L23/49827 , H01L2224/16 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K1/113 , H05K3/061 , H05K3/062 , H05K3/247 , H05K3/3484 , H05K3/4038 , H05K3/4602 , H05K3/4652 , H05K2201/0305 , H05K2201/035 , H01L2224/0401
摘要： A flip-chip joinable substrate having non-plated-on contact pads. The substrate has an external metal foil layer upon a dielectric layer upon a patterned internal metal layer having an internal contact area. An area of the external metal foil layer above the internal contact area is selected. A microvia cavity extending to the internal contact area is perforated centrally within the selected area and is filled with a mass of conductive paste forming an external contact pad. The external contact pad is used as an etch mask for removing the adjacent external metal foil.
摘要翻译：具有非电镀接触焊盘的倒装芯片可连接衬底。衬底在具有内部接触面积的图案化内部金属层上的介电层上具有外部金属箔层。选择内部接触区域上方的外部金属箔层的区域。延伸到内部接触区域的微孔腔在所选择的区域内中心穿孔，并且填充有形成外部接触焊盘的导电浆料块。外部接触焊盘用作蚀刻掩模以去除相邻的外部金属箔。

48. 发明授权

US06678949B2 Process for forming a multi-level thin-film electronic packaging structure 失效
标题翻译：用于形成多层薄膜电子封装结构的方法
公开(公告)号：US06678949B2
公开(公告)日：2004-01-20
申请号：US09886326
申请日：2001-06-21
申请人： Chandrika Prasad , Roy Yu , Richard L. Canull , Giulio DiGiacomo , Ajay P. Giri , Lewis S. Goldmann , Kimberley A. Kelly , Bouwe W. Leenstra , Voya R. Markovich , Eric D. Perfecto , Sampath Purushothaman , Joseph M. Sullivan
发明人： Chandrika Prasad , Roy Yu , Richard L. Canull , Giulio DiGiacomo , Ajay P. Giri , Lewis S. Goldmann , Kimberley A. Kelly , Bouwe W. Leenstra , Voya R. Markovich , Eric D. Perfecto , Sampath Purushothaman , Joseph M. Sullivan
IPC分类号： H05K334
CPC分类号： H01L21/6835 , H01L21/4857 , H01L23/16 , H01L23/49833 , H01L2221/68359 , H01L2221/68368 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H05K1/141 , H05K3/20 , H05K3/284 , H05K3/3436 , H05K3/467 , H05K7/023 , H05K2201/049 , H05K2201/10977 , H05K2201/2036 , H05K2203/0182 , Y02P70/613 , Y10T29/49126 , Y10T29/4913 , Y10T29/49133 , Y10T29/49144 , Y10T29/49149 , Y10T29/49165 , Y10T29/49169 , Y10T29/49174 , Y10T29/49211 , Y10T29/49213 , H01L2924/00 , H01L2924/00014
摘要： A structure for mounting electronic devices. The structure uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.
摘要翻译：一种用于安装电子设备的结构。该结构使用介于下面的载体和上覆薄膜之间的非导电的兼容间隔物。间隔件包括通孔的图形，其与载体和薄膜的相对表面上的相对互连匹配。以这种方式，焊接连接可以在通孔中延伸，以将薄膜电连接到载体上并平滑地形。在用于形成结构的相关方法中，薄膜建立在第一牺牲载体上，然后在第二牺牲载体上进一步处理，以防止其在其加工期间变形，膨胀或以其它方式受到不利影响。使用封闭的焊料接合工艺形成薄膜和载体之间的焊接连接。间隔件与层压卡一起使用以在携带薄膜的卡的部分上产生热应力释放结构。

49. 发明授权

US06569604B1 Blind via formation in a photoimageable dielectric material 失效
标题翻译：通过在可光成像的电介质材料中形成盲目
公开(公告)号：US06569604B1
公开(公告)日：2003-05-27
申请号：US09345723
申请日：1999-06-30
申请人： Anilkumar Chinuprasad Bhatt , Francis Joseph Downes, Jr. , Robert Lee Lewis , Voya R. Markovich
发明人： Anilkumar Chinuprasad Bhatt , Francis Joseph Downes, Jr. , Robert Lee Lewis , Voya R. Markovich
IPC分类号： G03C500
CPC分类号： H01L23/49816 , H01L23/49827 , H01L2224/16 , H05K3/0023 , H05K3/0035 , H05K3/4602 , H05K2201/09827 , H05K2203/1476
摘要： A blind via structure, and associated laser ablation methods of formation, that includes a blind via within a photoimageable dielectric (PID) layer on a substrate, such that the sidewall of the blind via makes an obtuse angle with the blind end of the blind via. The obtuse-angled sidewall may be formed by executing two processes in sequence. In the first process, photoimaging of the PID layer, with selective exposure to ultraviolet light, results in one or more blind vias having acute-angled sidewalls. The photoimaging cross links the PID material that had been selectively exposed to ultraviolet light such that a subsequent developing step removes PID material not cross linked, or weakly cross linked, to simultaneously form multiple blind vias having different sized openings. In the second process, laser ablation is selectively employed to remove the acute-angled sidewalls from particular blind vias in a way that forms replacement obtuse-angled sidewalls in the laser-ablated blind vias. Alternatively, the first process involving photoimaging may be omitted such that the second step involving laser ablation forms the entire obtuse-angled blind via. The resultant blind via structure includes at least one blind via having an obtuse-angled sidewall, and optionally, at least one blind via having an acute-angled sidewall.
摘要翻译：盲通孔结构和相关联的激光烧蚀消融方法，其包括在衬底上的可光成像电介质（PID）层内的盲通孔，使得盲通孔的侧壁与盲孔的盲端通过钝角。可以通过依次执行两个过程来形成钝角侧壁。在第一个过程中，通过选择性地暴露在紫外线下的PID层的光成像产生一个或多个具有锐角侧壁的盲孔。光学成像将选择性暴露于紫外线的PID材料交叉连接，使得随后的显影步骤除去未交联或弱交联的PID材料，以同时形成具有不同尺寸开口的多个盲孔。在第二过程中，激光烧蚀被选择性地用于在激光烧蚀的盲孔中形成置换钝角侧壁的方式从特定的盲孔中去除锐角侧壁。或者，可以省略涉及光成像的第一过程，使得涉及激光烧蚀的第二步骤形成整个钝角盲孔。所得到的盲通孔结构包括至少一个具有钝角侧壁的盲孔，并且可选地，至少一个具有锐角侧壁的盲孔。

50. 发明授权

US06495239B1 Dielectric structure and method of formation 失效
标题翻译：介电结构和形成方法
公开(公告)号：US06495239B1
公开(公告)日：2002-12-17
申请号：US09458291
申请日：1999-12-10
申请人： Anilkumar C. Bhatt , Stephen J. Fuerniss , Roy H. Magnuson , Voya R. Markovich
发明人： Anilkumar C. Bhatt , Stephen J. Fuerniss , Roy H. Magnuson , Voya R. Markovich
IPC分类号： B32B310
CPC分类号： B32B7/04 , B32B27/26 , B32B27/32 , B32B2250/40 , B32B2305/72 , H05K3/0023 , H05K3/4602 , H05K3/4623 , H05K3/4626 , H05K3/4641 , H05K2201/09509 , H05K2201/09536 , Y10S428/901 , Y10T428/24273 , Y10T428/28 , Y10T428/31511
摘要： A dielectric structure, wherein two fully cured photoimageable dielectric (PID) layers of the structure are nonadhesively interfaced by a partially cured PID layer. The partially cured PID layer includes a power plane sandwiched between a first partially cured PID sheet and a second partially cured PID sheet. The fully cured PID layers each include an internal power plane, a plated via having a blind end conductively coupled to the internal power plane, and a plated via passing through the fully cured PID layer. The dielectric structure may further include a first PID film partially cured and nonadhesively coupled to one of the fully cured PID layers. The dialectric structure may further include a second PID film partially cured and nonadhesively coupled to the other fully cured PID layer.
摘要翻译：一种电介质结构，其中该结构的两个完全固化的可光成像电介质（PID）层通过部分固化的PID层非粘性地接合。部分固化的PID层包括夹在第一部分固化的PID片和第二部分固化的PID片之间的动力平面。完全固化的PID层各自包括内部电源平面，具有导电耦合到内部电源平面的盲端的电镀通孔以及穿过完全固化的PID层的电镀通孔。电介质结构还可以包括部分固化并非粘性地耦合到完全固化的PID层之一的第一PID膜。所述方程式结构还可以包括部分固化并非粘性地耦合到另一完全固化的PID层的第二PID膜。

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