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41. 发明授权

US08171204B2 Intelligent solid-state non-volatile memory device (NVMD) system with multi-level caching of multiple channels 失效
标题翻译：智能固态非易失性存储器件（NVMD）系统具有多通道多级缓存
公开(公告)号：US08171204B2
公开(公告)日：2012-05-01
申请号：US12115128
申请日：2008-05-05
申请人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F13/00
CPC分类号： G06F12/1416 , G06F3/0664 , G06F12/0851 , G06F12/0866 , G06F12/0897 , G06F21/32 , G06F21/78 , G06F21/79 , G06F2212/2022 , Y02D10/13
摘要： A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.
摘要翻译：闪存系统存储由逻辑块地址（LBA）寻址的非易失性存储器件（NVMD）中的数据块。 NVBA将对LBA进行重新配置以进行磨损均衡和坏块重定位。 NVMD在由NVMD控制器访问的通道中进行交织。 NVMD控制器具有缓存存储在该通道中的NVMD中的块的控制器高速缓存，而NVMD还包含高速缓存。多级缓存可以减少访问延迟。电源由NVMD控制器中的电源控制器以多级管理，为NVMD内的电源管理器设置电源策略。闪存系统中的多个NVMD控制器可以各自控制多个NVMD通道。具有NVMD的闪存系统可能包括用于安全性的指纹读取器。

42. 发明授权

US07966462B2 Multi-channel flash module with plane-interleaved sequential ECC writes and background recycling to restricted-write flash chips 有权
标题翻译：具有平面交错顺序ECC的多通道闪存模块写入和背景回收到限制写入闪存芯片
公开(公告)号：US07966462B2
公开(公告)日：2011-06-21
申请号：US11871627
申请日：2007-10-12
申请人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
发明人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
IPC分类号： G06F12/02
CPC分类号： G06F12/0607 , G06F12/0246 , G06F2212/7201 , G06F2212/7203 , G06F2212/7205 , G06F2212/7208 , G11C16/0408 , G11C2211/5649
摘要： A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.
摘要翻译：使用由物理顺序地址计数器生成的平面，块和页面地址从闪存中恢复RAM映射表。 RAM映射表在使用从逻辑块索引的最低位提取的交错比特的物理顺序地址计数器产生的平面交织序列之后恢复。这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。物理顺序地址计数器通过在中间物理块位之前递增平面交织比特，然后将MSB重定位到中间物理块比特之上来生成物理块号。这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。还执行后台回收和ECC写入。

43. 发明授权

US07761653B2 Flash micro-controller with shadow boot-loader SRAM for dual-device booting of micro-controller and host 失效
标题翻译：闪存微控制器带有引导加载器的SRAM，用于微控制器和主机的双设备启动
公开(公告)号：US07761653B2
公开(公告)日：2010-07-20
申请号：US11875648
申请日：2007-10-19
申请人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
发明人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F9/441
摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The boot code includes an initial boot loader, boot code and a control program that are executed by the flash microcontroller, and an operating system OS image and an external-host control program that are executed by an external host. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A first-reset-read address from the external host is captured by the microcontroller during its boot sequence and stored in a mapping table along with a physical address of the block in the SRAM buffer with the operating system OS image and the external-host control program. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory.
摘要翻译：闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。引导代码包括由闪存微控制器执行的初始引导加载程序，引导代码和控制程序，以及由外部主机执行的操作系统OS映像和外部主机控制程序。外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。微控制器在其引导序列期间捕获来自外部主机的第一复位读取地址，并将其与SRAM缓冲器中具有操作系统OS映像和外部主机控制的块的物理地址一起存储在映射表中程序。引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。

44. 发明授权

US07690030B1 Electronic data flash card with fingerprint verification capability 有权
标题翻译：具有指纹验证功能的电子数据闪存卡
公开(公告)号：US07690030B1
公开(公告)日：2010-03-30
申请号：US11458987
申请日：2006-07-20
申请人： Abraham C. Ma , Sun-Teck See , Charles C. Lee , Edward W. Lee , Ming-Shiang Shen
发明人： Abraham C. Ma , Sun-Teck See , Charles C. Lee , Edward W. Lee , Ming-Shiang Shen
IPC分类号： G06F7/04
CPC分类号： G06F12/1416 , G06F21/32 , G06F21/34 , G06F21/78 , G06K19/07 , G06K19/07354
摘要： An electronic data flash card with fingerprint capability is accessible by an host computer, and includes a processing unit connected to a flash memory device that stores a data file and reference fingerprint data of a person authorized to access the data file, a fingerprint sensor for scanning the fingerprint of a user and for generating input fingerprint data that can be compared with the stored reference fingerprint data, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer.
摘要翻译：具有指纹能力的电子数据闪存卡可由主机访问，并且包括连接到闪存设备的处理单元，该闪存设备存储被授权访问数据文件的人员的数据文件和参考指纹数据，用于扫描的指纹传感器用户的指纹和用于生成可以与存储的参考指纹数据进行比较的输入指纹数据，以及激活以便建立与主计算机的通信的输入 - 输出接口电路。在一个实施例中，电子数据闪存卡使用USB输入/输出接口电路与主计算机进行通信。

45. 发明授权

US07620769B2 Recycling partially-stale flash blocks using a sliding window for multi-level-cell (MLC) flash memory 失效
标题翻译：使用多层单元（MLC）闪存的滑动窗口回收部分陈旧的闪存块
公开(公告)号：US07620769B2
公开(公告)日：2009-11-17
申请号：US11674645
申请日：2007-02-13
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/02
CPC分类号： H01R13/629 , G06F12/0246 , G06F12/1416 , G06F21/32 , G06F21/78 , G06F2212/1044 , G06F2212/7201 , G06F2212/7205 , G06F2212/7209 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： A sliding window of flash blocks is used to reduce wasted space occupied by stale data in a flash memory. The sliding window slides downward over a few flash blocks. The oldest block is examined for valid pages of data, and the valid pages are copied to the end of the sliding window so that the first block has only stale pages. The first block can then be erased and eventually re-used. A RAM usage table contains valid bits for pages in each block in the sliding window. A page's valid bit is changed from an erased, unwritten state to a valid state when data is written to the page. Later, when new host data replaces that data, the old page's valid bit is set to the stale state. A RAM stale-flags table keeps track of pages that are full of stale pages.
摘要翻译：闪存块的滑动窗口用于减少闪存中过时数据占用的浪费空间。滑动窗口向下滑过几个闪光块。检查最旧的块是否有效的数据页面，有效的页面被复制到滑动窗口的末尾，以便第一个块只有过时的页面。然后可以擦除第一个块并最终重新使用。 RAM使用表包含滑动窗口中每个块中页面的有效位。当数据写入页面时，页面的有效位从擦除的未写入状态更改为有效状态。之后，当新的主机数据替换该数据时，旧页面的有效位被设置为陈旧状态。 RAM陈旧标记表可以跟踪页面中已经有过时的页面。

46. 发明申请

US20080071973A1 ELECTRONIC DATA FLASH CARD WITH VARIOUS FLASH MEMORY CELLS 审中-公开
公开(公告)号：US20080071973A1
公开(公告)日：2008-03-20
申请号：US11864671
申请日：2007-09-28
申请人： David Q. Chow , Frank I. Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank I. Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/1416 , G06F21/32 , G06F21/78 , G06F2212/7202 , G06F2212/7208 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

47. 发明授权

US07771215B1 MLC COB USB flash memory device with sliding plug connector 失效
标题翻译： MLC COB USB闪存设备，带滑动插头连接器
公开(公告)号：US07771215B1
公开(公告)日：2010-08-10
申请号：US12171194
申请日：2008-07-10
申请人： Jim Chin-Nan Ni , Abraham C. Ma , David Nguyen , Charles C. Lee , Ming-Shiang Shen
发明人： Jim Chin-Nan Ni , Abraham C. Ma , David Nguyen , Charles C. Lee , Ming-Shiang Shen
IPC分类号： H01R13/44
CPC分类号： G06K19/07 , G06K19/07732
摘要： Briefly, a portable USB flash memory device is disclosed to include a Chip-On-Board COB Printed Circuit Board Assembly PCBA inside. The flash memory device is enclosed inside a housing structure with a sliding button to deploy the USB plug connector external to the housing structure. The flash memory device with Multi-Level-Cell MLC compatible is being able to connect to a host with a Universal Serial Bus USB interface.
摘要翻译：简而言之，公开了一种便携式USB闪存设备，其中包括板上COB印刷电路板组件PCBA。闪存设备被封装在具有滑动按钮的壳体结构内，以将壳体结构外部的USB插头连接器部署。具有Multi-Level-Cell MLC兼容的闪存设备能够使用通用串行总线USB接口连接到主机。

48. 发明授权

US07649743B2 Open-frame solid-state drive housing with intrinsic grounding to protect exposed chips 失效
标题翻译：开放式固态驱动器外壳，具有固有的接地保护裸露的芯片
公开(公告)号：US07649743B2
公开(公告)日：2010-01-19
申请号：US12043398
申请日：2008-03-06
申请人： Jim Chin-Nan Ni , Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
发明人： Jim Chin-Nan Ni , Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： H05K5/00
CPC分类号： G06F12/1416 , G06F3/0658 , G06F3/0679 , G06F21/32 , G06F21/78
摘要： An open-frame flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips, a controller chip, and a Serial AT-Attachment (SATA) connector soldered to it. The PCBA is only partially encased by left and right frames or by a U-shaped bracket frame. The frames have PCBA supports and guide posts that fit near edges of the PCBA. The frames do not cover the top and bottom of the PCBA, allowing chips on the PCBA to be ventilated by unblocked air flow. Screws that attach the PCBA to the frame have metal collars that ground the frame to the PCBA's ground plane. The screws form a current path to draw any electro-static-discharge (ESD) current off the frame and onto a PCBA ground. When the SATA connector is inserted into a host, the host ground sinks ESD currents collected by the open frame.
摘要翻译：开放式闪存驱动器具有焊接到其上的具有闪存芯片的印刷电路板组件（PCBA），控制器芯片和串行AT附件（SATA）连接器。 PCBA仅部分地被左右框架或U形支架框架包围。这些框架具有PCBA支撑和适合PCBA边缘附近的导向柱。框架不覆盖PCBA的顶部和底部，允许PCBA上的芯片通过未阻塞的气流通风。将PCBA连接到框架上的螺钉具有金属套环，将框架接地到PCBA的接地平面。螺钉形成电流通道，以将任何静电放电（ESD）电流从框架上取出并插入PCBA接地。当SATA连接器插入主机时，主机接地会吸收由开放框架收集的ESD电流。

49. 发明授权

US07649742B2 Thin flash-hard-drive with two-piece casing 失效
标题翻译：薄型闪存硬盘驱动器，带两片式外壳
公开(公告)号：US07649742B2
公开(公告)日：2010-01-19
申请号：US11309843
申请日：2006-10-11
申请人： Jim Chin-Nan Ni , Abraham C. Ma , Charles C. Lee , Ming-Shiang Shen
发明人： Jim Chin-Nan Ni , Abraham C. Ma , Charles C. Lee , Ming-Shiang Shen
IPC分类号： H05K1/14
CPC分类号： H05K5/0269
摘要： A flash-memory drive replaces a hard-disk drive using an integrated device electronics (IDE) interface. The flash drive has a printed-circuit board assembly (PCBA) with a circuit board with flash-memory chips and a controller chip. The controller chip includes an input/output interface circuit to an external computer over the IDE interface, and a processing unit to read blocks of data from the flash-memory chips. The PCBA is encased inside an upper case and a lower case, with an IDE connector that fits through and opening between the cases. The cases can be assembled with the PCBA by a snap-together, ultrasonic-press, screw-fastener, or thermal-bond adhesive method. Center lines formed on the inside of the cases fit between rows of flash-memory chips to improve case rigidity. The connector has two rows of pins that straddle the center line of the circuit board for a balanced design.
摘要翻译：闪存驱动器使用集成设备电子（IDE）接口替换硬盘驱动器。闪存驱动器具有带有闪存芯片的电路板和控制器芯片的印刷电路板组件（PCBA）。控制器芯片包括通过IDE接口连接到外部计算机的输入/输出接口电路，以及从闪速存储器芯片读取数据块的处理单元。 PCBA被封装在上壳体和下壳体内，并具有适合通过壳体和壳体之间打开的IDE连接器。这些情况可以通过卡扣，超声波压力机，螺纹紧固件或热粘合粘合剂方法与PCBA组装。形成在壳体内部的中心线适配在闪存芯片的行之间，以提高外壳刚度。连接器具有跨越电路板中心线的两排销，用于平衡设计。

50. 发明申请

US20080071977A1 ELECTRONIC DATA FLASH CARD WITH VARIOUS FLASH MEMORY CELLS 审中-公开
公开(公告)号：US20080071977A1
公开(公告)日：2008-03-20
申请号：US11929837
申请日：2007-10-30
申请人： David Q. Chow , Frank I. Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank I. Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/1416 , G06F21/32 , G06F21/78 , G06F2212/7202 , G06F2212/7208 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

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