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41. 发明授权

US07396570B2 Plasma enhanced chemical vapor deposition method of forming titanium silicide comprising layers 有权
公开(公告)号：US07396570B2
公开(公告)日：2008-07-08
申请号：US11394988
申请日：2006-03-30
申请人： Cem Basceri , Irina Vasilyeva , Ammar Derraa , Philip H. Campbell , Gurtej S. Sandhu
发明人： Cem Basceri , Irina Vasilyeva , Ammar Derraa , Philip H. Campbell , Gurtej S. Sandhu
IPC分类号： H01L21/4763 , H05H1/24
CPC分类号： H01L21/28518 , C23C16/42 , H01L21/28556
摘要： Chemical vapor deposition methods of forming titanium silicide including layers on substrates are disclosed. TiCl4 and at least one silane are first fed to the chamber at or above a first volumetric ratio of TiCl4 to silane for a first period of time. The ratio is sufficiently high to avoid measurable deposition of titanium silicide on the substrate. Alternately, no measurable silane is fed to the chamber for a first period of time. Regardless, after the first period, TiCl4 and at least one silane are fed to the chamber at or below a second volumetric ratio of TiCl4 to silane for a second period of time. If at least one silane was fed during the first period of time, the second volumetric ratio is lower than the first volumetric ratio. Regardless, the second feeding is effective to plasma enhance chemical vapor deposit a titanium silicide including layer on the substrate.

42. 发明授权

US07253076B1 Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers 有权
标题翻译：含有钌和钨的层的形成方法和集成电路结构
公开(公告)号：US07253076B1
公开(公告)日：2007-08-07
申请号：US09590795
申请日：2000-06-08
申请人： Vishnu K. Agarwal , Garo Derderian , Gurtej S. Sandhu , Weimin M. Li , Mark Visokay , Cem Basceri , Sam Yang
发明人： Vishnu K. Agarwal , Garo Derderian , Gurtej S. Sandhu , Weimin M. Li , Mark Visokay , Cem Basceri , Sam Yang
IPC分类号： H01L21/20
CPC分类号： H01L28/84 , H01L21/31637 , H01L28/55 , H01L28/65
摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.
摘要翻译：具有增加的电容的电容器包括增强的表面积（粗糙表面）导电层或与高介电常数材料相容的其它层。在一种方法中，用于这种电容器的增强表面积导电层是通过在高温或高于500℃，低压75托或更低，最理想的5托或更低的高温下处理氧化钌层形成的，产生具有至少约100埃的平均特征尺寸的纹理表面的粗糙钌层。初始氧化钌层可以通过化学气相沉积技术或溅射技术等来提供。该层可以形成在下面的导电层上。处理可以在惰性环境或还原环境中进行。可以在处理期间或之后使用供氮环境或供氮还原环境以钝化钌以改善与高介电常数电介质材料的相容性。氧化环境中的处理也可以进行以钝化粗糙层。可以使用粗糙化的钌层来形成增强表面积的导电层。所形成的增强表面积导电层可以在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。在另一种方法中，提供氮化钨层作为这种电容器的第一电极。电容器或至少氮化钨层被退火以增加电容器的电容。

43. 发明授权

US07192828B2 Capacitor with high dielectric constant materials and method of making 有权
标题翻译：具有高介电常数材料和制作方法的电容器
公开(公告)号：US07192828B2
公开(公告)日：2007-03-20
申请号：US10819420
申请日：2004-04-07
申请人： Cem Basceri , Gurtej S. Sandhu , Sam Yang
发明人： Cem Basceri , Gurtej S. Sandhu , Sam Yang
IPC分类号： H01L21/8242
CPC分类号： H01L28/75 , H01L21/02178 , H01L21/02183 , H01L21/02197 , H01L21/02271 , H01L21/31604 , H01L21/31683 , H01L27/10811 , H01L28/55
摘要： A stabilized capacitor using non-oxide electrodes and high dielectric constant oxide dielectric materials and methods of making such capacitors and their incorporation into DRAM cells is provided. A preferred method includes providing a non-oxide electrode, oxidizing an upper surface of the non-oxide electrode, depositing a high dielectric constant oxide dielectric material on the oxidized surface of the non-oxide electrode, and depositing an upper layer electrode on the high dielectric constant oxide dielectric material.
摘要翻译：提供了使用非氧化物电极和高介电常数氧化物电介质材料的稳定电容器以及制造这种电容器并将其并入DRAM单元的方法。优选的方法包括提供非氧化物电极，氧化非氧化物电极的上表面，在非氧化物电极的氧化表面上沉积高介电常数氧化物电介质材料，以及在高电极上沉积上层电极介电常数氧化物介电材料。

44. 发明授权

US07150789B2 Atomic layer deposition methods 失效
标题翻译：原子层沉积法
公开(公告)号：US07150789B2
公开(公告)日：2006-12-19
申请号：US10208314
申请日：2002-07-29
申请人： Paul J. Castovillo , Cem Basceri , Garo J. Derderian , Gurtej S. Sandhu
发明人： Paul J. Castovillo , Cem Basceri , Garo J. Derderian , Gurtej S. Sandhu
IPC分类号： C30B23/00
CPC分类号： C30B25/14 , C23C14/0641 , C23C14/081 , C23C16/34 , C23C16/403 , C23C16/45527 , C23C16/45531
摘要： An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to the substrate within the atomic layer deposition chamber effective to form a first monolayer on the substrate. After forming the first monolayer, a reactive intermediate gas is flowed to the substrate within the deposition chamber. The reactive intermediate gas is capable of reaction with an intermediate reaction by-product from the first precursor flowing under conditions of the reactive intermediate gas flowing. After flowing the reactive intermediate gas, a second precursor gas is flowed to the substrate within the deposition chamber effective to form a second monolayer on the first monolayer. Other aspects and implementations are contemplated.
摘要翻译：原子层沉积方法包括将半导体衬底定位在原子层沉积室内。第一前体气体流到原子层沉积室内的衬底，有效地在衬底上形成第一单层。在形成第一单层之后，反应性中间气体流到沉积室内的衬底。反应性中间体气体能够与在反应性中间体气体流动的条件下流动的第一前体的中间反应副产物反应。在流动反应性中间气体之后，第二前体气体流到沉积室内的衬底，有效地在第一单层上形成第二单层。考虑了其他方面和实现。

45. 发明授权

US07144779B2 Method of forming epitaxial silicon-comprising material 有权
标题翻译：形成外延含硅材料的方法
公开(公告)号：US07144779B2
公开(公告)日：2006-12-05
申请号：US10931924
申请日：2004-09-01
申请人： Nirmal Ramaswamy , Gurtej S. Sandhu , Cem Basceri , Eric R. Blomiley
发明人： Nirmal Ramaswamy , Gurtej S. Sandhu , Cem Basceri , Eric R. Blomiley
IPC分类号： H01L21/336
CPC分类号： H01L29/66787 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L29/66553 , H01L29/66666 , H01L29/7827 , H01L29/78642
摘要： The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成外延含硅材料的方法和形成垂直晶体管的方法。在一个实施方案中，形成外延含硅材料的方法包括提供包括单晶材料的衬底。单晶材料的第一部分向外暴露，而单晶材料的第二部分被掩蔽。第一含硅层从第一部分的暴露的单晶材料而不是被掩蔽的第二部分的单晶材料外延生长。在生长第一含硅层之后，单晶材料的第二部分被未掩蔽。然后从第一含硅层和第二部分的未掩模的单晶材料外延生长第二含硅层。考虑了其他方面和实现。

46. 发明授权

US07132355B2 Method of forming a layer comprising epitaxial silicon and a field effect transistor 有权
公开(公告)号：US07132355B2
公开(公告)日：2006-11-07
申请号：US10932129
申请日：2004-09-01
申请人： Nirmal Ramaswamy , Gurtej S. Sandhu , Cem Basceri , Eric R. Blomiley
发明人： Nirmal Ramaswamy , Gurtej S. Sandhu , Cem Basceri , Eric R. Blomiley
IPC分类号： H01L21/44
CPC分类号： H01L29/66787 , H01L21/0237 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L29/66742 , H01L29/78642
摘要： This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.

47. 发明授权

US06987055B2 Methods for deposition of semiconductor material 失效
标题翻译：半导体材料沉积方法
公开(公告)号：US06987055B2
公开(公告)日：2006-01-17
申请号：US10755000
申请日：2004-01-09
申请人： Eric R. Blomiley , Gurtej S. Sandhu , Cem Basceri , Nirmal Ramaswamy
发明人： Eric R. Blomiley , Gurtej S. Sandhu , Cem Basceri , Nirmal Ramaswamy
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639
摘要： The invention includes a method for selective deposition of semiconductor material. A substrate is placed within a reaction chamber. The substrate comprises a first surface and a second surface. The first and second surfaces are exposed to a semiconductor material precursor under conditions in which growth of semiconductor material from the precursor comprises a lag phase prior to a growth phase, and under which it takes longer for the growth phase to initiate on the second surface than on the first surface. The exposure of the first and second surfaces is conducted for a time sufficient for the growth phase to occur on the first surface, but not long enough for the growth phase to occur on the second surface.
摘要翻译：本发明包括半导体材料的选择性沉积方法。将基板放置在反应室内。基板包括第一表面和第二表面。第一表面和第二表面在半导体材料前体暴露于其中来自前体的半导体材料的生长在生长阶段之前包含滞后期的条件下，并且在该阶段生长阶段在第二表面上开始需要更长时间比在第一个表面。进行第一表面和第二表面的曝光足够长的时间，以使生长阶段在第一表面上发生，但是不足以使生长相发生在第二表面上。

48. 发明授权

US06962824B2 Method for controlling deposition of dielectric films 失效
公开(公告)号：US06962824B2
公开(公告)日：2005-11-08
申请号：US10925560
申请日：2004-08-25
申请人： Cem Basceri , Dan Gealy , Gurtej S. Sandhu
发明人： Cem Basceri , Dan Gealy , Gurtej S. Sandhu
IPC分类号： C23C16/40 , C23C16/52 , H01L21/314 , H01L21/316 , H01L21/00
CPC分类号： H01L21/02271 , C23C16/409 , C23C16/52 , H01L21/02197 , H01L21/31691
摘要： A method for controlling stoichiometry of dielectric films, e.g., BST films, preferably formed at low deposition temperatures. A deposition process may use an adjustment in oxidizer flow and/or partial pressure, the provision of a hydrogen-containing component, an adjustment in hydrogen-containing component flow and/or partial pressure, an adjustment in deposition pressure, and/or a modification of system component parameters (e.g., heating a shower head or adjusting a distance between a shower head of the deposition system and a wafer upon which the film is to be deposited), to control the characteristics of the dielectric film, e.g., film stoichiometry.

49. 发明授权

US06767806B2 METHOD OF FORMING A PATTERNED SUBSTANTIALLY CRYSTALLINE TA2O5 COMPRISING MATERIAL, AND METHOD OF FORMING A CAPACITOR HAVING A CAPACITOR DIELECTRIC REGION COMPRISING SUBSTANTIALLY CRYSTALLINE TA2O5 COMPRISING MATERIAL 失效
标题翻译：形成包含材料的大型结晶TA2O5的形成方法以及形成包含包含材料的大量结晶TA2O5的电容器介电区域的电容器的方法
公开(公告)号：US06767806B2
公开(公告)日：2004-07-27
申请号：US10243386
申请日：2002-09-13
申请人： Cem Basceri , Garo J. Derderian , Mark R. Visokay , John M. Drynan , Gurtej S. Sandhu
发明人： Cem Basceri , Garo J. Derderian , Mark R. Visokay , John M. Drynan , Gurtej S. Sandhu
IPC分类号： H01L2120
CPC分类号： H01L21/31122 , H01L21/28061 , H01L21/28518 , H01L21/28556 , H01L21/28568 , H01L21/31604 , H01L21/32051 , H01L27/10811 , H01L27/10888 , H01L28/90 , H01L29/6659
摘要： In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta2O5 comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta2O5 comprising layer over a semiconductive substrate. The layer is exposed to WF6 under conditions effective to etch substantially amorphous Ta2O5 from the substrate. In one implementation, the layer is exposed to WF6 under conditions effective to both etch substantially amorphous Ta2O5 from the substrate and deposit a tungsten comprising layer over the substrate during the exposing.
摘要翻译：部分地，公开了半导体处理方法，在衬底上沉积含钨层的方法，在衬底上沉积含氮化钨的层的方法，在衬底上沉积包含硅化钨的层的方法，形成晶体管栅极的方法在衬底上划线，形成图案化的基本上结晶的Ta 2 O 5的材料的方法，以及形成包含基本上结晶的Ta 2 O 5的材料的电容器电介质区域的方法。在一个实施方案中，半导体处理方法包括在半导体衬底上形成包含基本非晶态的Ta 2 O 5层。该层在有效从底物上蚀刻基本无定形Ta 2 O 5的条件下暴露于WF6。在一个实施方案中，该层在有效地从衬底上蚀刻基本上无定形Ta 2 O 5的条件下暴露于WF6，并在曝光期间在衬底上沉积含钨层。

50. 发明授权

US06753271B2 Atomic layer deposition methods 有权
标题翻译：原子层沉积法
公开(公告)号：US06753271B2
公开(公告)日：2004-06-22
申请号：US10222282
申请日：2002-08-15
申请人： Demetrius Sarigiannis , Garo J. Derderian , Cem Basceri , Gurtej S. Sandhu , F. Daniel Gealy , Chris M. Carlson
发明人： Demetrius Sarigiannis , Garo J. Derderian , Cem Basceri , Gurtej S. Sandhu , F. Daniel Gealy , Chris M. Carlson
IPC分类号： H01L2144
CPC分类号： H01L21/32051 , C23C16/4404 , C23C16/4405 , C23C16/45531 , C23C16/45534 , H01L21/02178 , H01L21/02186 , H01L21/0228 , H01L21/28562 , H01L21/3141 , H01L21/31616
摘要： The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a semiconductor substrate within an atomic layer deposition chamber. On the substrate, an intermediate composition monolayer is formed, followed by a desired deposited composition from reaction with the intermediate composition, collectively from flowing multiple different composition deposition precursors to the substrate within the deposition chamber. A material adheres to a chamber internal component surface from such sequentially forming. After such sequentially forming, a reactive gas flows to the chamber which is different in composition from the multiple different deposition precursors and which is effective to react with such adhering material. After the reactive gas flowing, such sequentially forming is repeated. Further implementations are contemplated.
摘要翻译：本发明包括在基板上形成沉积的组合物层的原子层沉积方法。该方法包括将半导体衬底定位在原子层沉积室内。在基材上形成中间组合物单层，随后是与中间体组合物反应所需的沉积组合物，统称为将多种不同的组合物沉积前体流到沉积室内的基底。材料粘附到室内部件表面，从而依次形成。在这种顺序形成之后，反应性气体流入到与多种不同的沉积前体不同的组合物中，并有效地与这种粘附材料反应。在反应气体流动之后，重复这种顺序形成。考虑进一步的实现。

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