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41. 发明申请

US20070048438A1 THERMOCHROMIC COATINGS 审中-公开
标题翻译：热敏涂料
公开(公告)号：US20070048438A1
公开(公告)日：2007-03-01
申请号：US11424821
申请日：2006-06-16
申请人： Ivan Parkin , Troy Manning
发明人： Ivan Parkin , Troy Manning
IPC分类号： C23C28/00 , B05D5/12
CPC分类号： C03C17/245 , C01G31/00 , C01P2002/50 , C03C2217/218 , C03C2218/152 , C23C16/405
摘要： The present invention provides the use of atmospheric pressure chemical vapour deposition (APCVD) for producing a film of thermochmmic transition metal-doped vanadium (iN) oxide on a substrate. Specifically, the invention prevides a method of producing a film of thermochromic transition metal-doped vanadium (IV) oxide on a substrate by atmospheric pressure chemical vapour deposition comprising the steps of: (i) reacting together (a) a vanadium precursor, (b) a transition metal dopant precursor, and (c) an oxygen precursor in an atmospheric pressure chemical vapour deposition reactor to form thermochromic transition metal-doped vanadium (IV) oxide, and (ii) depositing the thermochromic transition metal-doped vanadium (IV) oxide onto the substrate. A preferred transition metal dopant is tungsten. The invention also provides transition metal-doped vanadium (TV) oxide, films thereof and substrates (e.g., glass substrates) coated with a film of transition metal-doped vanadium (IV) oxide. Intelligent window systems, infrared modulators and data storage devices comprising such substrates are also provided.
摘要翻译：本发明提供大气压化学气相沉积（APCVD）用于在衬底上生产热过渡金属掺杂钒（iN）的薄膜的用途。具体地说，本发明预先通过大气压化学气相沉积法在基底上制造热致变色金属过渡金属掺杂氧化钒（IV）的膜的方法，包括以下步骤：（i）使（a）钒前体，（b ）过渡金属掺杂剂前体，和（c）在大气压化学气相沉积反应器中的氧前体，以形成热变色金属掺杂的氧化钒（IV），和（ii）沉积热变色过渡金属掺杂的钒（IV）氧化物到基板上。优选的过渡金属掺杂剂是钨。本发明还提供了过渡金属掺杂的钒（TV）氧化物，其膜和涂覆有过渡金属掺杂的氧化钒（IV）的膜的衬底（例如，玻璃衬底）。还提供了包括这种基板的智能窗系统，红外调制器和数据存储装置。

42. 发明授权

US06407955B2 Integrated circuit having an on-board reference generator 有权
标题翻译：具有板载参考发生器的集成电路
公开(公告)号：US06407955B2
公开(公告)日：2002-06-18
申请号：US09844952
申请日：2001-04-27
申请人： Troy Manning
发明人： Troy Manning
IPC分类号： G11C2900
CPC分类号： G11C29/12
摘要： An integrated circuit includes a differential amplifier having a first terminal that is operable to receive an input signal and having a second terminal. The integrated circuit also includes a reference circuit that generates a reference signal on the second terminal of the amplifier. During testing of the integrated circuit, the reference circuit can be activated to generate the reference signal such that a tester need not supply it as a test signal. During normal operation, however, either the reference circuit can generate the reference signal or the reference signal can be supplied by an external source.
摘要翻译：集成电路包括具有可操作以接收输入信号并具有第二端子的第一端子的差分放大器。集成电路还包括在放大器的第二端子上产生参考信号的参考电路。在集成电路测试期间，可以激活参考电路以产生参考信号，使得测试仪不需要将其作为测试信号提供。然而，在正常操作期间，参考电路可以产生参考信号，或者参考信号可以由外部源提供。

43. 发明授权

US6137312A Voltage level translator 有权
公开(公告)号：US6137312A
公开(公告)日：2000-10-24
申请号：US327040
申请日：1999-06-07
申请人： Troy Manning
发明人： Troy Manning
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/00361
摘要： A translator includes an initial circuit device configured to charge a translator output to a first voltage level in response to a change in an input signal. The translator further includes a sensing device configured to detect the output's potential approaching the first voltage level and smoothly shift charging functions over to a secondary circuit device, which will continue to charge the output up to a second voltage level.

44. 发明授权

US5953269A Method and apparatus for remapping addresses for redundancy 有权
标题翻译：重新映射冗余地址的方法和装置
公开(公告)号：US5953269A
公开(公告)日：1999-09-14
申请号：US146586
申请日：1998-09-03
申请人： Troy Manning
发明人： Troy Manning
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/76 , G11C29/808 , G11C29/81
摘要： A semiconductor memory device includes a memory array having first and second columns, each column having a plurality of memory locations associated therewith and being identified by first and second column addresses, respectively. Column address decoding circuitry receives column address signals and selects at least one column memory array. The column address decoding circuitry is programmable such that the first column is identified by the second column address and the second column may be identified by the first column address.
摘要翻译：半导体存储器件包括具有第一和第二列的存储器阵列，每列具有与其相关联的多个存储器位置，并且分别由第一和第二列地址识别。列地址解码电路接收列地址信号并选择至少一个列存储器阵列。列地址解码电路是可编程的，使得第一列由第二列地址标识，第二列可以由第一列地址来标识。

45. 发明授权

US5657293A Integrated circuit memory with back end mode disable 失效
标题翻译：集成电路存储器，后端模式禁用
公开(公告)号：US5657293A
公开(公告)日：1997-08-12
申请号：US518157
申请日：1995-08-23
申请人： Todd Merritt , Troy Manning
发明人： Todd Merritt , Troy Manning
IPC分类号： G11C11/401 , G11C7/10 , G11C17/16
CPC分类号： G11C7/1045
摘要： A memory circuit is described which can operate in one of a number of operating modes. The operating mode of the memory circuit can be changed in a non-volatile manner after the memory circuit is packaged to reduce production scrap or meet market demands. Disable circuitry is described which includes an anti-fuse that can be externally selectively blown to disable an operating mode. Control circuitry included in the memory circuit enables a new operating mode after the first operating mode is disable. A method of selectively disabling an operating mode is described. A hierarchical scheme is also described for enabling a new operating mode from a group of operating modes, for example page-mode, extended data output (EDO), or burst EDO.
摘要翻译：描述了可以以多种操作模式之一操作的存储器电路。在存储器电路被封装以减少生产废料或满足市场需求之后，可以以非易失性的方式改变存储器电路的工作模式。描述禁止电路，其包括可以从外部选择性地吹制以禁用操作模式的反熔丝。包含在存储器电路中的控制电路在第一操作模式被禁用之后启用新的操作模式。描述了选择性地禁用操作模式的方法。还描述了分层方案，用于从一组操作模式启用新的操作模式，例如页面模式，扩展数据输出（EDO）或突发EDO。

46. 发明申请

US20060198180A1 DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES 失效
标题翻译：分布式写入数据驱动器，用于冲突访问记忆
公开(公告)号：US20060198180A1
公开(公告)日：2006-09-07
申请号：US11419166
申请日：2006-05-18
申请人： Todd Merritt , Troy Manning
发明人： Todd Merritt , Troy Manning
IPC分类号： G11C11/24
CPC分类号： G11C7/109 , G06F12/0638 , G06F2212/2022 , G11C7/1021 , G11C7/1024 , G11C7/1027 , G11C7/1039 , G11C7/1045 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C7/22 , G11C11/407 , G11C11/4076 , G11C11/4096
摘要： An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating toggling Read/Write control line at cycle frequency. Control line transition terminates access and initializes another burst access. Write cycle times are maximized thereby allowing increases in burst mode operating frequencies. Logic near sense amplifiers control write-data drivers thereby providing maximum write times without crossing current during I/O line equilibration. By gating global write-enable signals with global equilibrate signals locally at sense amps, local write-cycle control signals are provided and valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory. For nonburst mode, write begins following end of equilibration cycle to provide maximum write time without interfering with subsequent access-cycle address setup time.
摘要翻译：地址选通锁存第一个地址。突发周期会在内部增加地址选通信号。只有在每次突发访问开始时才需要新的内存地址。读/写命令每次突发存取发出一次，消除了循环频率下的切换读/写控制线。控制线转换终止访问并初始化另一个突发访问。写周期时间最大化，从而允许突发模式工作频率的增加。读出放大器附近的逻辑控制写入数据驱动器，从而在I / O线平衡期间提供最大的写入时间，而无需交叉电流。通过在感测放大器上本地使用全局平衡信号选通全局写使能信号，提供本地写周期控制信号，并且基本上在整个周期时间内减去突发存取存储器中的I / O线平衡周期。对于非突发模式，写入开始于平衡周期结束后提供最大写入时间，而不会影响随后的访问周期地址建立时间。

47. 发明申请

US20050242827A1 Contact pad arrangement on a die 有权
标题翻译：模具上的接触垫排列
公开(公告)号：US20050242827A1
公开(公告)日：2005-11-03
申请号：US11177892
申请日：2005-07-08
申请人： Troy Manning
发明人： Troy Manning
IPC分类号： G01R31/02 , G01R31/28 , G01R31/319 , G06F11/273
CPC分类号： G01R31/31905 , G01R31/2884 , G06F11/2733
摘要： An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access with testing equipment. Signals from the redundant bond pad are biased to ground during normal operations of the integrated device. In order to test the relevant internal circuitry, a voltage is applied to a Test Mode Enable bond pad, overcoming the bias that grounds the redundant bond pad. In addition, the signal from the Test Mode Enable bond pad serves to ground any transmission from the main bond pad. As a result, the redundant bond pad may be used to test the relevant internal circuitry given its accessible location in relation to the testing equipment.
摘要翻译：如果用于该电路的主接合焊盘难以用测试设备访问，则集成设备包括用于访问内部电路的冗余接合焊盘。来自冗余接合焊盘的信号在集成器件的正常操作期间被偏置到接地。为了测试相关的内部电路，将一个电压施加到测试模式使能焊盘，克服接地冗余焊盘的偏压。此外，来自测试模式使能接合焊盘的信号用于接地主接合焊盘的任何传输。因此，冗余接合焊盘可用于测试相对于测试设备的可访问位置的相关内部电路。

48. 发明授权

US06288954B1 Integrated circuit having an on-board reference generator 有权
标题翻译：具有板载参考发生器的集成电路
公开(公告)号：US06288954B1
公开(公告)日：2001-09-11
申请号：US09233774
申请日：1999-01-19
申请人： Troy Manning
发明人： Troy Manning
IPC分类号： G11C2900
CPC分类号： G11C29/12
摘要： An integrated circuit includes a differential amplifier having a first terminal that is operable to receive an input signal and having a second terminal. The integrated circuit also includes a reference circuit that generates a reference signal on the second terminal of the amplifier. During testing of the integrated circuit, the reference circuit can be activated to generate the reference signal such that a tester need not supply it as a test signal. During normal operation, however, either the reference circuit can generate the reference signal or the reference signal can be supplied by an external source.
摘要翻译：集成电路包括具有可操作以接收输入信号并具有第二端子的第一端子的差分放大器。集成电路还包括在放大器的第二端子上产生参考信号的参考电路。在集成电路测试期间，可以激活参考电路以产生参考信号，使得测试仪不需要将其作为测试信号提供。然而，在正常操作期间，参考电路可以产生参考信号，或者参考信号可以由外部源提供。

49. 发明授权

US6108251A Method and apparatus for remapping memory addresses for redundancy 有权
标题翻译：用于重新映射存储器地址以用于冗余的方法和装置
公开(公告)号：US6108251A
公开(公告)日：2000-08-22
申请号：US364947
申请日：1999-07-30
申请人： Troy Manning
发明人： Troy Manning
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/76 , G11C29/808 , G11C29/81
摘要： A semiconductor memory device includes a memory array having first and second columns, each column having a plurality of memory locations associated therewith and being identified by first and second column addresses, respectively. Column address decoding circuitry receives column address signals and selects at least one column memory array. The column address decoding circuitry is programmable such that the first column may be identified by the second column address and the second column may be identified by the first column address.
摘要翻译：半导体存储器件包括具有第一和第二列的存储器阵列，每列具有与其相关联的多个存储器位置，并且分别由第一和第二列地址识别。列地址解码电路接收列地址信号并选择至少一个列存储器阵列。列地址解码电路是可编程的，使得第一列可以由第二列地址识别，第二列可以由第一列地址来标识。

50. 发明授权

US5910734A Voltage level translator 失效
公开(公告)号：US5910734A
公开(公告)日：1999-06-08
申请号：US803343
申请日：1997-02-20
申请人： Troy Manning
发明人： Troy Manning
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/00361
摘要： A translator includes an initial circuit device configured to charge a translator output to a first voltage level in response to a change in an input signal. The translator further includes a sensing device configured to detect the output's potential approaching the first voltage level and smoothly shift charging functions over to a secondary circuit device, which will continue to charge the output up to a second voltage level.

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