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41. 发明授权

US06169432A High voltage switch for providing voltages higher than 2.5 volts with transistors made using a 2.5 volt process 有权
标题翻译：高压开关用于提供高于2.5伏特的电压，使用2.5伏工艺制造的晶体管
公开(公告)号：US06169432A
公开(公告)日：2001-01-02
申请号：US09188778
申请日：1998-11-09
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： H03B100
CPC分类号： H03K17/102
摘要： A voltage switch is provided made up of 2.5 volt process transistors which tolerate a maximum gate to source, gate to drain, or drain to source voltage of 2.7 volts. The voltage switch transistors are arranged to switch between a voltage, such as 2.5 volts, and a much higher voltage, such as 4.5 volts. In one embodiment (350), the voltage switch includes an input provided to the source of an NMOS cascode connected transistor (360). An inverter (354) connects the source of the NMOS cascode (360) to the source of another NMOS cascode (361). A cascode transistor is defined as being connected so that it is turned on and off by varying source voltage with the gate voltage fixed, rather than varying gate voltage. Gates of the cascodes (360, 361) are connected to Vcc (2.5 volts). PMOS cascode transistors (362) and (363) connect the drains of respective cascode transistors (360) and (361) to PMOS transistors (364) and (365). The PMOS transistors (364) and (365) have sources connected to 4.5 volts. A PMOS transistor (366) has a gate tied to the drain of cascode (361) and provides Vcc to the switch output (n10). A PMOS transistor (368) has a gate tied to the gate of transistor 365 and supplies 4.5 volts to the switch output (n10). In operation, the switch (350) functions to selectively transition its output (n10) between Vcc and 4.5 volts without applying greater than 2.7 volts from the gate to source, gate to drain, or source to drain of any of its transistors.
摘要翻译：提供由2.5伏过程晶体管组成的电压开关，其容许最大的栅极到源极，栅极到漏极或漏极到源极电压为2.7伏特。电压开关晶体管被布置成在诸如2.5伏特的电压和诸如4.5伏特的高得多的电压之间切换。在一个实施例（350）中，电压开关包括提供给NMOS共源共栅连接晶体管（360）的源极的输入端。反相器（354）将NMOS共源共栅（360）的源极连接到另一个NMOS共源共栅（361）的源极。共源共栅晶体管被定义为连接，使得其通过在栅极电压固定的情况下改变源极电压来导通和关断，而不是改变栅极电压。级联（360,361）的栅极连接到Vcc（2.5伏特）。 PMOS级联晶体管（362）和（363）将各自的共源共栅晶体管（360）和（361）的漏极连接到PMOS晶体管（364）和（365）。 PMOS晶体管（364）和（365）具有连接到4.5伏特的源极。 PMOS晶体管（366）具有连接到共源共栅（361）的漏极的栅极，并向开关输出（n10）提供Vcc。 PMOS晶体管（368）具有连接到晶体管365的栅极的栅极，并向开关输出（n10）提供4.5伏特。在操作中，开关（350）用于选择性地将其输出（n10）在Vcc和4.5V之间转变，而不施加大于2.7伏的栅极至源极，栅极至漏极或其任何晶体管的源极到漏极。

42. 发明授权

US6163175A High voltage detector to control a power supply voltage pump for a 2.5 volt semiconductor process device 失效
标题翻译：高压检测器用于控制2.5伏半导体工艺装置的电源电压泵
公开(公告)号：US6163175A
公开(公告)日：2000-12-19
申请号：US276990
申请日：1999-03-26
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： H02M3/07 , H03K5/24 , H03K5/153
CPC分类号： H03K5/2481 , H02M3/073
摘要： A high voltage detector circuit (FIG. 2) maintains a voltage (V.sub.2) on a reference line driven by a charge pump by turning the charge pump on with a signal (PUMPON) when the reference line voltage (V.sub.2) drops below a reference voltage (V.sub.1) plus a CMOS transistor threshold voltage. The high voltage detector is further configured to use transistors which have a maximum gate to drain, or gate to source voltage which exceeds the pin supply voltage to the chip. The high voltage detector includes comparators made up of a series of current mirrors driven by weak current sources enabling the circuit to use a minimum amount of power.
摘要翻译：高电压检测器电路（图2）通过在基准线电压（V2）下降到参考电压以下时，用信号（PUMPON）转动电荷泵来维持由电荷泵驱动的参考线上的电压（V2）（V1）加上CMOS晶体管阈值电压。高电压检测器还被配置为使用具有最大栅极漏极或栅极至源极电压的晶体管，栅极至源极电压超过芯片的引脚电源电压。高电压检测器包括由弱电流源驱动的一系列电流镜构成的比较器，使得电路能够使用最小量的功率。

43. 发明授权

US5808942A Field programmable gate array (FPGA) having an improved configuration memory and look up table 失效
标题翻译：具有改进的配置存储器和查找表的现场可编程门阵列（FPGA）
公开(公告)号：US5808942A
公开(公告)日：1998-09-15
申请号：US659941
申请日：1996-06-07
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： H03K19/177 , G11C7/00
CPC分类号： H03K19/1776 , H03K19/17704
摘要： An FPGA including SRAM memory cells, each having a latch configured so that both read and write signals are provided through the data path connection. By providing both read and write through the data path, the FPGA further includes only a single decoder to control pass gates connected to the memory cells during read and write. To prevent voltages during write from damaging pass gates in the data path, the FPGA further includes a modified power supply to provide voltages ranging from V.sub.DD to V.sub.SS to the memory cell transistors during read, while providing a reduced voltage range during write to enable memory cell states to more easily be altered.
摘要翻译：包括SRAM存储器单元的FPGA，每个存储单元具有被配置为使得通过数据路径连接提供读取和写入信号的锁存器。通过提供读取和写入数据路径，FPGA进一步仅包含一个解码器，以便在读取和写入期间控制连接到存储器单元的通孔。为了防止在写入过程中的电压损坏数据通路中的通过门，FPGA还包括修改后的电源，以在读取期间提供从VDD到VSS的电压到存储单元晶体管，同时在写入期间提供降低的电压范围以使存储单元状态更容易被改变。

44. 发明授权

US5594687A Completely complementary MOS memory cell with tunneling through the NMOS and PMOS transistors during program and erase 失效
标题翻译：完全互补的MOS存储单元，在编程和擦除期间通过NMOS和PMOS晶体管隧穿
公开(公告)号：US5594687A
公开(公告)日：1997-01-14
申请号：US447991
申请日：1995-05-23
申请人： Jonathan Lin , Radu Barsan , Bradley A. Sharpe-Geisler
发明人： Jonathan Lin , Radu Barsan , Bradley A. Sharpe-Geisler
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： G11C16/045 , G11C16/0441 , H01L27/115 , G11C2216/10
摘要： Circuitry added to CMOS memory cell configured to enable tunneling through its PMOS and NMOS transistors, the circuitry preventing leakage current during programming. The circuitry includes a separate NMOS pass gate for connecting the source of the NMOS transistor of the CMOS cell to Vss. The gate of the NMOS pass gate is controlled to turn off the NMOS transistor during programming through the PMOS transistor to prevent current loss on the Vss line. The NMOS pass gate further provides a means for enabling or disabling the NMOS transistor making the CMOS cell useful as an array cell for a PAL device.
摘要翻译：电路添加到CMOS存储器单元中，配置为能够通过其PMOS和NMOS晶体管进行隧穿，该电路可防止编程期间的漏电流。该电路包括用于将CMOS单元的NMOS晶体管的源极连接到Vss的单独的NMOS通孔。在通过PMOS晶体管的编程期间，NMOS栅极的栅极被控制为关闭NMOS晶体管，以防止Vss线上的电流损耗。 NMOS栅极进一步提供用于启用或禁用NMOS晶体管的装置，其使得CMOS单元可用作PAL器件的阵列单元。

45. 发明授权

US5084404A Gate array structure and process to allow optioning at second metal mask only 失效
标题翻译：门阵列结构和过程仅允许在第二金属掩模上进行选择
公开(公告)号：US5084404A
公开(公告)日：1992-01-28
申请号：US685586
申请日：1991-04-15
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： H01L21/768 , H01L23/525 , H01L27/118
CPC分类号： H01L23/5256 , H01L21/76892 , H01L27/118 , H01L2924/0002 , Y10S257/909
摘要： A structure and method for forming a semicustom integrated circuit in which customization can be performed using only a single masking step. Vias in an insulation layer between first and second metal are made larger than first metal lines so that after deposition of second metal, a final patterning etch can remove not only portions of the second metal to leave interconnect lines but can also remove second metal within any exposed vias and additionally remove first metal in order to disconnect selected portions of first metal lines. In order for the final etch step not to remove portions of the substrate, an extra step of planarizing the insulation layer between first and second metal is provided. The large vias provided by the structure and method also allow for shrinking the size of first and second metal lines and thus shrinking the metal line width required by the design rules for the entire semiconductor structure.
摘要翻译：用于形成半定制集成电路的结构和方法，其中可以仅使用单个掩蔽步骤来进行定制。在第一和第二金属之间的绝缘层中的通孔被制成大于第一金属线，使得在沉积第二金属之后，最终图案化蚀刻不仅可以去除第二金属的部分以留下互连线，而且还可以去除任何暴露的通孔并且另外去除第一金属以便断开第一金属线的选定部分。为了最终蚀刻步骤不去除衬底的部分，提供了在第一和第二金属之间平坦化绝缘层的额外步骤。由结构和方法提供的大的通孔也允许收缩第一和第二金属线的尺寸，从而缩小整个半导体结构的设计规则所需的金属线宽度。

46. 发明授权

US06218857B1 Variable sized line driving amplifiers for input/output blocks (IOBs) in FPGA integrated circuits 失效
标题翻译： FPGA集成电路中输入/输出块（IOB）的可变尺寸线路驱动放大器
公开(公告)号：US06218857B1
公开(公告)日：2001-04-17
申请号：US09198796
申请日：1998-11-24
申请人： Bradley A. Sharpe-Geisler , Giap Tran
发明人： Bradley A. Sharpe-Geisler , Giap Tran
IPC分类号： H03K19177
CPC分类号： H03K19/17744 , H03K19/09429 , H03K19/1778
摘要： An input/output block (IOB) in a field programmable gate array (FPGA) efficiently provides signals to an inter-connect network in the FPGA device. The IOB is one of a plurality of IOBs positioned about a plurality of variable grain blocks (VGBs) in the FPGA device. The IOB includes a first sized line driving amplifier for generating a first signal at a first IOB output. A second sized line driving amplifier generates a second signal at a second IOB output. The first sized line driving amplifier includes a PMOS transistor having a polysilicon gate width of approximately 20 microns and an NMOS transistor having a polysilicon gate width of approximately 10 microns. The second sized line driving amplifier includes a PMOS transistor, an NMOS transistor, a NAND gate, NOR gate and inverter. The second sized amplifier PMOS transistor has a polysilicon gate width of approximately 35 microns and an NMOS transistor having a polysilicon gate width of approximately 15 microns. The IOB has multiple outputs connected to various inter-connect network resources. An IOB output is coupled to a (1) direct connect line, (2) NOR line, (3) dendrite line and (4) MaxL line. The various lines may have a predetermined length and/or capacitance. The various sized amplifiers in the IOB are sized dependent upon the respective line types connected to the IOB. The various sized amplifiers allow for the reduction of undue signal propagation delays or unnecessarily large sized amplifiers.
摘要翻译：现场可编程门阵列（FPGA）中的输入/输出块（IOB）有效地向FPGA器件中的互连网络提供信号。 IOB是围绕FPGA器件中的多个可变粒子块（VGB）定位的多个IOB之一。 IOB包括用于在第一IOB输出处产生第一信号的第一尺寸线驱动放大器。第二尺寸线驱动放大器在第二IOB输出端产生第二信号。第一尺寸线驱动放大器包括具有约20微米的多晶硅栅极宽度的PMOS晶体管和具有约10微米的多晶硅栅极宽度的NMOS晶体管。第二尺寸线驱动放大器包括PMOS晶体管，NMOS晶体管，NAND门，NOR门和反相器。第二尺寸放大器PMOS晶体管具有大约35微米的多晶硅栅极宽度和具有约15微米的多晶硅栅极宽度的NMOS晶体管。 IOB具有连接到各种互连网络资源的多个输出。 IOB输出耦合到（1）直接连接线，（2）NOR线，（3）枝晶线和（4）MaxL线。各种线可以具有预定的长度和/或电容。 IOB中的各种尺寸的放大器的大小取决于连接到IOB的各种线路类型。各种尺寸的放大器允许减少不适当的信号传播延迟或不必要的大尺寸放大器。

47. 发明授权

US6124733A Input buffer providing virtual hysteresis 失效
标题翻译：输入缓冲区提供虚拟滞后
公开(公告)号：US6124733A
公开(公告)日：2000-09-26
申请号：US996442
申请日：1997-12-22
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： H03K3/3565 , H03K19/003 , H03B1/00 , H03K3/037 , H03K19/0175
CPC分类号： H03K3/3565
摘要： An input buffer includes a first CMOS inverter (400) made up of a PMOS transistor (602) connecting Vdd to the buffer output and an NMOS transistor (604) connecting the buffer output to Vss. NMOS transistors (404) and (414) have with series connected source to drain paths to connect the buffer output to Vss in conjunction with transistor (604) of inverter (400). PMOS transistors (402) and (412) have series connected source to drain paths connecting Vdd to the buffer output in conjunction with transistor (602). To control transistors (402, 404, 412 and 414) an inverter (420) is connected from the buffer output to the gates of transistors (402 and 404), and inverters (431, 432, 433, and 440) are connected between the buffer input and the gates of transistors (412 and 414). After a low to high buffer input transition above a level (H1), the inverter (420) will transition and the NMOS transistors (404 and 414) will turn on together to create a path to Vss with transistor (604) of inverter (400) to decrease the buffer threshold to (H2). After the buffer input rises further above a threshold (H1A) of inverter (431) combined with inverter (440), inverter (433) will turn off transistor (414) to set the buffer threshold back to (H1). After a high to low buffer input transition below a level (H1), the inverter (420) will transition and the PMOS transistors (402 and 412) will both be on together to create a path to Vdd with transistor (602) of inverter (400) to increase the buffer threshold to (H3). After the buffer input falls further below a threshold (H1B) of inverters (431) and (440), inverter (433) will turn off transistor (412) to set the buffer threshold back to (H1).
摘要翻译：输入缓冲器包括由将Vdd连接到缓冲器输出的PMOS晶体管（602）和将缓冲器输出连接到Vss的NMOS晶体管（604）构成的第一CMOS反相器（400）。 NMOS晶体管（404）和（414）具有串联连接的源极到漏极路径，以将缓冲器输出连接到逆变器（400）的晶体管（604）。 PMOS晶体管（402）和（412）具有串联连接的源至漏极路径，连接Vdd与晶体管（602）的缓冲器输出。为了控制晶体管（402,404,412和414），逆变器（420）从缓冲器输出连接到晶体管（402和404）的栅极，并且反相器（431,432,433和440）连接在晶体管缓冲器输入和晶体管（412和414）的栅极。在高于电平（H1）的低至高缓冲器输入转换之后，反相器（420）将转变，并且NMOS晶体管（404和414）将一起导通以产生到Vss的路径，其中逆变器（400）的晶体管（604））将缓冲器阈值降低到（H2）。在缓冲器输入进一步升高到与逆变器（440）组合的逆变器（431）的阈值（H1A）之上，反相器（433）将关闭晶体管（414）以将缓冲器阈值设置为（H1）。在低电平（H1）的高到低的缓冲器输入转换之后，反相器（420）将转变，并且PMOS晶体管（402和412）将两者都在一起，以产生与变换器晶体管（602）的Vdd的路径 400）将缓冲区阈值增加到（H3）。在缓冲器输入进一步低于反相器（431）和（440）的阈值（H1B）之后，反相器（433）将关闭晶体管（412）以将缓冲器阈值设置为（H1）。

48. 发明授权

US6072351A Output buffer for making a 5.0 volt compatible input/output in a 2.5 volt semiconductor process 失效
标题翻译：输出缓冲器，用于在2.5伏半导体工艺中进行5.0伏兼容的输入/输出
公开(公告)号：US6072351A
公开(公告)日：2000-06-06
申请号：US912763
申请日：1997-08-18
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： H03K19/003 , H03K5/08
CPC分类号： H03K19/00315
摘要： An output buffer including transistors which tolerate a maximum gate to source, gate to drain, or drain to source voltage ("the maximum tolerable voltage"), such as 2.7 volts, the transistors being configured to produce an output voltage significantly higher than the maximum tolerable voltage. The output buffer includes pull up transistors having source to drain paths connected in series to connect a voltage supply higher than the maximum tolerable voltage to the buffer output. The buffer further includes pull down transistors having source to drain paths connected in series to connect the buffer output to ground. The buffer further includes power supply circuitry to apply gate voltages to the pull up and pull down transistors so that the voltage potential from the source to drain of each of the pull up and pull down transistors is less than the maximum tolerable voltage. The power supply circuitry further controls gate voltages so that neither the gate to source, nor the gate to drain voltage for each of the pull up and pull down transistors exceeds the maximum tolerable voltage. Additionally, the power supply circuitry is itself configured so that voltage across the gate to source, gate to drain, or source to drain for each of its transistors does not exceed the maximum tolerable voltage. The power supply circuitry further provides a tristate configuration so that voltages can be applied to the buffer output from an external source exceeding the maximum tolerable voltage without a voltage from the gate to source, gate to drain, or source to drain of a transistor in the output buffer exceeding the maximum tolerable voltage.
摘要翻译：输出缓冲器包括容纳最大栅极至源极，栅极至漏极或漏极至源极电压（“最大可容忍电压”）的晶体管，例如2.7伏，晶体管被配置为产生明显高于最大值的输出电压耐受电压输出缓冲器包括具有串联连接的源极至漏极路径的上拉晶体管，以将高于最大容许电压的电压源连接到缓冲器输出端。该缓冲器还包括具有串联连接的源极至漏极路径的下拉晶体管，以将缓冲器输出端连接到地。缓冲器还包括电源电路，以将栅极电压施加到上拉和下拉晶体管，使得每个上拉和下拉晶体管的源极到漏极的电压电位小于最大容许电压。电源电路还控制栅极电压，使得每个上拉和下拉晶体管的栅极到源极以及栅极到漏极电压都不超过最大容许电压。此外，电源电路本身被配置成使得栅极到源极，栅极到漏极或者其晶体管的每个晶体管的源极到漏极之间的电压不超过最大容许电压。电源电路还提供三态配置，使得电压可以从超过最大容许电压的外部源施加到缓冲器输出，而没有电压从栅极到源极，栅极到漏极或源极到漏极中的晶体管的电压输出缓冲器超过最大容许电压。

49. 发明授权

US5912550A Power converter with 2.5 volt semiconductor process components 有权
标题翻译：电源转换器采用2.5伏半导体工艺组件
公开(公告)号：US5912550A
公开(公告)日：1999-06-15
申请号：US196080
申请日：1998-11-19
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： G05F1/575 , G05F3/26 , G05F1/56
CPC分类号： G05F1/575 , G05F3/262
摘要： A power converter provides a voltage reference (Vdd) to a plurality of transistors on an integrated circuit with a limited voltage swing when a load is connected and removed. The power converter includes an opamp (100) having an input (+) receiving a voltage reference (V.sub.DIOD), an input (-) connected to a resistor divider (102, 104) and an output driving the gate of a transistor (110). The transistor (110) has a source to drain path providing a 3.3 volt supply (NV3EXT) to an output node (n2) which supplies Vdd. The output node (n2) is connected back to the resistor divider (102,104) and to the source of a cascode transistor (300). The cascode (300) is connected with cascode (302) to form a current mirror which is interconnected with transistor (304) and capacitor (306) to slow the response at node (n7) to transitions at the output node (n2). Cascode (300) drives a current mirror (314, 316). The operational amplifier (100) functions to control the gate voltage of transistor (110) to maintain the voltage Vdd at a constant value. With significant loading to the output, after the loading is removed, cascode (300) will turn on to cause transistor (316) to limit the voltage swing of Vdd until opamp (100) can return Vdd to a constant value.
摘要翻译：当负载被连接和移除时，功率转换器在集成电路上具有有限的电压摆幅的多个晶体管提供电压基准（Vdd）。功率转换器包括具有接收电压参考（VDIOD）的输入（+）的运算放大器（100），连接到电阻分压器（102,104）的输入（ - ）和驱动晶体管（110）的栅极的输出，。晶体管（110）具有向提供Vdd的输出节点（n2）提供3.3伏电源（NV3EXT）的源极到漏极路径。输出节点（n2）连接回电阻分压器（102,104）并连接到共源共栅晶体管（300）的源极。共源共栅（300）与共源共栅（302）连接以形成与晶体管（304）和电容器（306）互连的电流镜，以将节点（n7）处的响应减慢到输出节点（n2）处的转变。 Cascode（300）驱动电流镜（314,316）。运算放大器（100）用于控制晶体管（110）的栅极电压以将电压Vdd维持在恒定值。随着对输出的显着负载，在去除负载之后，共源共栅（300）将导通，以使晶体管（316）限制Vdd的电压摆幅，直到运算放大器（100）可以将Vdd返回到恒定值。

50. 发明授权

US5760609A Clock signal providing circuit with enable and a pulse generator with enable for use in a block clock circuit of a programmable logic device 失效
标题翻译：具有使能的时钟信号提供电路和可用于可编程逻辑器件的块时钟电路的脉冲发生器
公开(公告)号：US5760609A
公开(公告)日：1998-06-02
申请号：US666193
申请日：1996-06-19
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： H03K3/037 , H03K3/356 , H03K19/177 , H03K19/21 , H03K19/00
CPC分类号： H03K19/1774 , H03K19/17704 , H03K19/1778 , H03K19/215 , H03K3/037 , H03K3/0375 , H03K3/356156
摘要： A clock signal providing circuit with enable and pulse generator with enable for use in a block clock circuit of a programmable logic device (PLD), the block clock circuit for allocating multiple clock signals to each macrocell of the PLD. The clock signal providing circuit includes circuitry which functions to change states in response to a pin clock signal when an enable signal is active, and to maintain its current state when the enable signal is inactive. The pulse generator includes circuitry which functions to provide a pulse at a first edge of a pin clock signal if an enable signal remains active from prior to receipt of the first edge of the pin clock signal.
摘要翻译：一种具有使能和脉冲发生器的时钟信号提供电路，其可用于可编程逻辑器件（PLD）的块时钟电路中，块时钟电路用于向PLD的每个宏单元分配多个时钟信号。时钟信号提供电路包括当使能信号有效时响应于引脚时钟信号而改变状态的电路，并且当使能信号无效时保持其当前状态。脉冲发生器包括用于在引脚时钟信号的第一边缘处提供脉冲的电路，如果使能信号在接收到引脚时钟信号的第一沿之前保持有效。

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