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41. 发明申请

US20050064716A1 Plasma removal of high k metal oxide 审中-公开
标题翻译：等离子体去除高k金属氧化物
公开(公告)号：US20050064716A1
公开(公告)日：2005-03-24
申请号：US10951646
申请日：2004-09-28
申请人： Hong Lin , Shiqun Gu , Wai Lo , James Elmer
发明人： Hong Lin , Shiqun Gu , Wai Lo , James Elmer
IPC分类号： H01L21/28 , H01L21/311 , H01L29/51 , H01L29/80 , H01L21/302 , H01L21/461 , H01L31/112
CPC分类号： H01L29/518 , H01L21/28185 , H01L21/28202 , H01L21/31111 , H01L29/51 , H01L29/511 , H01L29/513 , H01L29/517
摘要： A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an in-situ plasma species that causes structural damage to the exposed portions of the high k layer. The structurally damaged exposed portions of the high k layer are wet etched to leave the high k gate insulation layer.
摘要翻译：在基板上的集成电路中形成高k栅极绝缘层的方法。将高k层沉积在衬底上，并用掩模图案以限定高k栅极绝缘层和高k层的暴露部分。高k层的暴露部分经受原位等离子体物质，这导致对高k层的暴露部分的结构损伤。高k层的结构损坏的暴露部分被湿蚀刻以留下高k栅极绝缘层。

42. 发明授权

US06674092B1 Thin film CMOS calibration standard having protective cover layer 失效
公开(公告)号：US06674092B1
公开(公告)日：2004-01-06
申请号：US10194578
申请日：2002-07-12
申请人： Wai Lo , David Chan
发明人： Wai Lo , David Chan
IPC分类号： H01L2358
CPC分类号： H01L22/34 , G01B11/0616
摘要： Embodiments of the invention include a calibration standard for semiconductor metrology tools. The standard comprises a substrate having a surface with a calibration layer formed thereon. A protective layer is formed over the underlying calibration layer. The calibration layer and protective layer are each formed to precise tolerances. The invention also includes methods for forming a calibration standard for semiconductor metrology tools.

43. 发明授权

US09105469B2 Defect mitigation structures for semiconductor devices 有权
标题翻译：半导体器件的缺陷缓解结构
公开(公告)号：US09105469B2
公开(公告)日：2015-08-11
申请号：US13172880
申请日：2011-06-30
申请人： Zubin P. Patel , Tracy Helen Fung , Jinsong Tang , Wai Lo , Arun Ramamoorthy
发明人： Zubin P. Patel , Tracy Helen Fung , Jinsong Tang , Wai Lo , Arun Ramamoorthy
IPC分类号： H01L29/12 , H01L21/02
CPC分类号： H01L21/02433 , H01L21/02381 , H01L21/02439 , H01L21/02447 , H01L21/0245 , H01L21/02458 , H01L21/02505 , H01L21/0251 , H01L21/0254
摘要： A method and a semiconductor device for incorporating defect mitigation structures are provided. The semiconductor device comprises a substrate, a defect mitigation structure comprising a combination of layers of doped or undoped group IV alloys and metal or non-metal nitrides disposed over the substrate, and a device active layer disposed over the defect mitigation structure. The defect mitigation structure is fabricated by depositing one or more defect mitigation layers comprising a substrate nucleation layer disposed over the substrate, a substrate intermediate layer disposed over the substrate nucleation layer, a substrate top layer disposed over the substrate intermediate layer, a device nucleation layer disposed over the substrate top layer, a device intermediate layer disposed over the device nucleation layer, and a device top layer disposed over the device intermediate layer. The substrate intermediate layer and the device intermediate layer comprise a distribution in their compositions along a thickness coordinate.
摘要翻译：提供了一种用于并入缺陷缓解结构的方法和半导体器件。半导体器件包括衬底，包括掺杂或未掺杂IV族合金的层的组合以及设置在衬底上的金属或非金属氮化物的组合的缺陷缓解结构，以及设置在缺陷缓解结构上的器件活性层。通过沉积一个或多个缺陷缓解层来制造缺陷缓解结构，所述缺陷缓解层包括设置在衬底上的衬底成核层，设置在衬底成核层上的衬底中间层，设置在衬底中间层上的衬底顶层，器件成核层设置在衬底顶层上方，设置在器件成核层上的器件中间层，以及设置在器件中间层上方的器件顶层。衬底中间层和器件中间层沿其厚度坐标包括其组成中的分布。

44. 发明申请

US20130001641A1 Defect Mitigation Structures For Semiconductor Devices 有权
标题翻译：半导体器件的缺陷缓解结构
公开(公告)号：US20130001641A1
公开(公告)日：2013-01-03
申请号：US13172880
申请日：2011-06-30
申请人： Zubin P. Patel , Tracy Helen Fung , Jinsong Tang , Wai Lo , Arun Ramamoorthy
发明人： Zubin P. Patel , Tracy Helen Fung , Jinsong Tang , Wai Lo , Arun Ramamoorthy
IPC分类号： H01L29/02 , H01L21/20
CPC分类号： H01L21/02433 , H01L21/02381 , H01L21/02439 , H01L21/02447 , H01L21/0245 , H01L21/02458 , H01L21/02505 , H01L21/0251 , H01L21/0254
摘要： A method and a semiconductor device for incorporating defect mitigation structures are provided. The semiconductor device comprises a substrate, a defect mitigation structure comprising a combination of layers of doped or undoped group IV alloys and metal or non-metal nitrides disposed over the substrate, and a device active layer disposed over the defect mitigation structure. The defect mitigation structure is fabricated by depositing one or more defect mitigation layers comprising a substrate nucleation layer disposed over the substrate, a substrate intermediate layer disposed over the substrate nucleation layer, a substrate top layer disposed over the substrate intermediate layer, a device nucleation layer disposed over the substrate top layer, a device intermediate layer disposed over the device nucleation layer, and a device top layer disposed over the device intermediate layer. The substrate intermediate layer and the device intermediate layer comprise a distribution in their compositions along a thickness coordinate.
摘要翻译：提供了一种用于并入缺陷缓解结构的方法和半导体器件。半导体器件包括衬底，包括掺杂或未掺杂IV族合金的层的组合以及设置在衬底上的金属或非金属氮化物的组合的缺陷缓解结构，以及设置在缺陷缓解结构上的器件活性层。通过沉积一个或多个缺陷缓解层来制造缺陷缓解结构，所述缺陷缓解层包括设置在衬底上的衬底成核层，设置在衬底成核层上的衬底中间层，设置在衬底中间层上的衬底顶层，器件成核层设置在衬底顶层上方，设置在器件成核层上的器件中间层，以及设置在器件中间层上方的器件顶层。衬底中间层和器件中间层沿其厚度坐标包括其组成中的分布。

45. 发明授权

US08202779B2 Methods for forming a memory cell having a top oxide spacer 有权
标题翻译：形成具有顶部氧化物间隔物的存储单元的方法
公开(公告)号：US08202779B2
公开(公告)日：2012-06-19
申请号：US12891310
申请日：2010-09-27
申请人： Shenqing Fang , Angela Hui , Gang Xue , Alexander Nickel , Kashmir Sahota , Scott Bell , Chun Chen , Wai Lo
发明人： Shenqing Fang , Angela Hui , Gang Xue , Alexander Nickel , Kashmir Sahota , Scott Bell , Chun Chen , Wai Lo
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/792
摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.
摘要翻译：公开了制造具有间隔层的半导体存储单元的方法。一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

46. 发明授权

US07916529B2 Pin diode device and architecture 有权
标题翻译： pin二极管器件和架构
公开(公告)号：US07916529B2
公开(公告)日：2011-03-29
申请号：US12370932
申请日：2009-02-13
申请人： Wai Lo , Christie Marrian , Tzu-Ning Fang , Sameer Haddad
发明人： Wai Lo , Christie Marrian , Tzu-Ning Fang , Sameer Haddad
IPC分类号： G11C11/36
CPC分类号： H01L27/1021 , G11C5/04 , G11C11/36 , H01L27/24 , H01L29/868
摘要： A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.
摘要翻译：提供采用一个或多个半导体PIN二极管的存储架构。存储器采用包括掩埋位/字线和PIN二极管的衬底。 PIN二极管包括非本征半导体区域，位/字线的一部分和位于非固有区域和位/字线部分之间的本征半导体区域。

47. 发明申请

US20100208517A1 PIN DIODE DEVICE AND ARCHITECTURE 有权
标题翻译： PIN二极管器件和架构
公开(公告)号：US20100208517A1
公开(公告)日：2010-08-19
申请号：US12370932
申请日：2009-02-13
申请人： Wai Lo , Christie Marrian , Tzu-Ning Fang , Sameer Haddad
发明人： Wai Lo , Christie Marrian , Tzu-Ning Fang , Sameer Haddad
IPC分类号： G11C11/36 , H01L29/868 , H01L21/425 , G11C7/00
CPC分类号： H01L27/1021 , G11C5/04 , G11C11/36 , H01L27/24 , H01L29/868
摘要： A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.
摘要翻译：提供采用一个或多个半导体PIN二极管的存储架构。存储器采用包括掩埋位/字线和PIN二极管的衬底。 PIN二极管包括非本征半导体区域，位/字线的一部分和位于非固有区域和位/字线部分之间的本征半导体区域。

48. 发明授权

US07619272B2 Bi-axial texturing of high-K dielectric films to reduce leakage currents 失效
标题翻译：高K电介质膜的双轴纹理化以减少漏电流
公开(公告)号：US07619272B2
公开(公告)日：2009-11-17
申请号：US11007392
申请日：2004-12-07
申请人： Wai Lo , Sey-Shing Sun , Wilbur Catabay
发明人： Wai Lo , Sey-Shing Sun , Wilbur Catabay
IPC分类号： H01L29/76
CPC分类号： H01L29/51 , C23C14/226 , C23C14/3442 , C23C14/46 , C23C16/486 , H01L21/02189 , H01L21/02266 , H01L21/28194 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645
摘要： The present invention is directed to a method of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a material used in forming the high-K dielectric film and also using an ion beam to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.
摘要翻译：本发明涉及制造在膜的晶界处具有高度晶体取向度的高K电介质膜的方法。所公开的方法包括提供衬底，然后沉积用于形成高K电介质膜的材料，并且还使用离子束来辅助优选形成具有选定结晶取向的晶格。所得的电介质膜在膜的晶界处具有高度的结晶取向度。另一公开的方法包括提供衬底，然后将材料成角度地沉积到衬底上，以帮助优先形成具有选定结晶取向的晶格。所得的电介质膜在膜的晶界处具有高度的结晶取向度。

49. 发明申请

US20090101963A1 SPLIT CHARGE STORAGE NODE INNER SPACER PROCESS 有权
标题翻译：分离式充电储存装置内部空间过程
公开(公告)号：US20090101963A1
公开(公告)日：2009-04-23
申请号：US11873822
申请日：2007-10-17
申请人： Minghao Shen , Shenqing Fang , Wai Lo , Christie R.K. Marrian , Chungho Lee , Ning Cheng , Fred Cheung , Huaqiang Wu
发明人： Minghao Shen , Shenqing Fang , Wai Lo , Christie R.K. Marrian , Chungho Lee , Ning Cheng , Fred Cheung , Huaqiang Wu
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7923 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42344
摘要： Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.
摘要翻译：提供了在半导体衬底上形成包含两个分开的次光刻电荷存储节点的存储单元的方法。这些方法可以包括通过使用间隔物形成技术形成两个分裂的亚光刻电荷存储节点。通过去除第一多晶硅层的暴露部分，同时留下被间隔物保护的第一多晶硅层的部分，该方法可以提供两个分裂的次光刻的第一多晶硅栅极。此外，通过去除电荷存储层的暴露部分，同时保留由两个分割子光刻第一多晶硅栅极保护的电荷存储层的部分，该方法可以提供电荷存储层的两个分开的窄部分，其随后形成两个拆分次光刻电荷存储节点。

50. 发明申请

US20080308882A1 APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW 有权
标题翻译：门盖边缘应用于更换门盖晶体管流程中的门长度CD
公开(公告)号：US20080308882A1
公开(公告)日：2008-12-18
申请号：US12140773
申请日：2008-06-17
申请人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
发明人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
IPC分类号： H01L29/00
CPC分类号： H01L29/49 , G02B6/3897 , G02B6/445 , H01L29/51 , H02G15/117
摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.
摘要翻译：保持良好限定的栅极堆叠轮廓的方法，沉积或生长均匀的栅极电介质，并且通过在虚拟栅极蚀刻之后和间隔物工艺之前沉积的惰性绝缘衬垫来维持栅极长度CD控制。衬垫材料对用于去除伪栅极氧化物的湿化学品是选择性的，从而防止间隔区域中的底切。该方法旨在使金属栅极电极技术成为与现有制造环境兼容的可行技术，用于多代CMOS晶体管，包括属于65nm，45nm和25nm技术节点的CMOS晶体管，这些晶体管正在用于模拟，数字或混合信号集成电路，用于通信，娱乐，教育和安全产品等各种应用。

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