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41. 发明申请

US20130224919A1 METHOD FOR MAKING GATE-OXIDE WITH STEP-GRADED THICKNESS IN TRENCHED DMOS DEVICE FOR REDUCED GATE-TO-DRAIN CAPACITANCE 审中-公开
标题翻译：用于制造具有步进厚度的栅极氧化物的方法，用于降低栅极 - 漏电电容的固化DMOS器件
公开(公告)号：US20130224919A1
公开(公告)日：2013-08-29
申请号：US13406814
申请日：2012-02-28
申请人： Yongping Ding , Sik Lui , Anup Bhalla
发明人： Yongping Ding , Sik Lui , Anup Bhalla
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/66719 , H01L29/66734
摘要： A method for making gate-oxide with step-graded thickness (S-G GOX) in a trenched DMOS device is proposed. First, a substrate is provided and a silicon oxide-silicon nitride-silicon oxide (ONO) protective composite layer is formed atop. Second, an upper interim trench (UIT), an upper trench protection wall (UTPW) and a lower interim trench (LIT) are created into the substrate. Third, the substrate material surrounding the LIT is shaped and oxidized into a desired thick-oxide-layer of thickness T1 and depth D1. Fourth, previously formed UTPW is stripped off from the device in progress, then a thin-gate-oxide of thickness T2 where T2
摘要翻译：提出了一种在沟槽DMOS器件中制造具有阶梯分级厚度（S-G GOX）的栅极氧化物的方法。首先，设置基板，在顶部形成氧化硅 - 氮化硅 - 氧化硅（ONO）保护复合层。第二，在衬底中产生上部中间沟槽（UIT），上沟槽保护壁（UTPW）和下部临时沟槽（LIT）。第三，围绕LIT的衬底材料成形并氧化成厚度T1和深度D1的所需厚氧化物层。第四，先前形成的UTPW从正在进行的器件剥离，然后在UIT的垂直表面上形成T2

42. 发明授权

US08324683B2 Oxide terminated trench MOSFET with three or four masks 有权
标题翻译：具有三个或四个掩模的氧化物端接沟槽MOSFET
公开(公告)号：US08324683B2
公开(公告)日：2012-12-04
申请号：US13367916
申请日：2012-02-07
申请人： Sik Lui , Anup Bhalla
发明人： Sik Lui , Anup Bhalla
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/3081 , H01L21/31 , H01L21/32133 , H01L21/76224 , H01L27/088 , H01L29/0638 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/66666 , H01L29/66734 , H01L29/7811 , H01L29/7827
摘要： An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.
摘要翻译：氧化物终端半导体器件可以包括多个栅极沟槽，栅极流道和绝缘体端接沟槽。栅极沟槽位于有源区域中。每个栅极沟槽包括导电栅电极。绝缘体端接沟槽位于围绕有源区域的端接区域中。绝缘体端接沟槽填充有绝缘体材料以形成用于半导体器件的绝缘子端子。该装置可以使用三掩模或四掩模工艺制成。

43. 发明授权

US07800169B2 Power MOS device 有权
标题翻译：功率MOS器件
公开(公告)号：US07800169B2
公开(公告)日：2010-09-21
申请号：US11900603
申请日：2007-09-11
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中;延伸穿过源和主体的栅沟槽，漏极，设置在栅极沟槽中的栅极，具有沟槽壁的源体接触沟槽和沿着沟槽壁布置的抗穿孔植入物。制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成栅极沟槽，通过硬掩模，在栅极沟槽中沉积栅极材料，去除硬掩模以留下栅极形成具有沟槽壁并形成抗穿孔植入物的源体接触沟槽。

44. 发明申请

US20080001220A1 Power MOS device 有权
标题翻译：功率MOS器件
公开(公告)号：US20080001220A1
公开(公告)日：2008-01-03
申请号：US11900616
申请日：2007-09-11
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中;延伸穿过源和主体的栅沟槽，漏极，设置在栅极沟槽中的栅极，具有沟槽壁的源体接触沟槽和沿着沟槽壁布置的抗穿孔植入物。制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成栅极沟槽，通过硬掩模，在栅极沟槽中沉积栅极材料，去除硬掩模以留下栅极形成具有沟槽壁并形成抗穿孔植入物的源体接触沟槽。

45. 发明申请

US20060273379A1 MOSFET using gate work function engineering for switching applications 审中-公开
标题翻译： MOSFET采用门极功能工程用于开关应用
公开(公告)号：US20060273379A1
公开(公告)日：2006-12-07
申请号：US11146499
申请日：2005-06-06
申请人： Anup Bhalla , Sik Lui
发明人： Anup Bhalla , Sik Lui
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/4916 , H01L29/4983 , H01L29/66734 , H01L29/7811
摘要： This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by manufacturing a MOSFET with a higher gate work function by implementing a P-doped gate in an N-MOSFET device. The P-type gate increases the threshold voltage and shifts the C-Vds characteristics. The reduced Cgd thus achieves the purpose of suppressing the shoot through and resolve the difficulties discussed above. Unlike the conventional techniques, the reduction of the capacitance Cgd is achieved without requiring complicated fabrication processes and control of the recess electrode.
摘要翻译：本发明公开了一种新的MOSFET器件。通过在N-MOSFET器件中实现P掺杂栅极，MOSFET器件具有通过制造具有较高栅极功能功能的MOSFET获得的改进的操作特性。 P型栅极增加阈值电压并移位C-Vds特性。因此，减少的Cgd实现了抑制拍摄的目的，并解决了上述困难。与常规技术不同，实现了电容Cgd的减小，而不需要复杂的制造工艺和凹陷电极的控制。

46. 发明申请

US20060208788A1 MOSFET for synchronous rectification 有权
标题翻译： MOSFET用于同步整流
公开(公告)号：US20060208788A1
公开(公告)日：2006-09-21
申请号：US11083470
申请日：2005-03-18
申请人： Anup Bhalla , Sik Lui
发明人： Anup Bhalla , Sik Lui
IPC分类号： H03K17/687
CPC分类号： H01L27/088 , H01L27/0629 , H01L29/7803 , H01L29/7813 , H01L2223/6644 , H01L2224/16145 , H01L2224/45144 , H01L2224/48247 , H03K17/165 , H01L2924/00
摘要： This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.
摘要翻译：本发明公开了一种新的MOSFET器件。 MOSFET器件具有通过将低阻抗的并联FET连接到MOSFET器件而实现的改进的操作特性。并联FET分流瞬态电流。分流FET用于防止MOSFET器件无意中导通。当在MOSFET器件的漏极处发生大的电压瞬变时，可能会发生MOSFET的无意开启。通过将分流FET的栅极连接到MOSFET器件的漏极，在电路操作期间在正确的时间点提供低阻抗路径，以分流电流而不需要任何外部电路。

47. 发明授权

US08896131B2 Cascode scheme for improved device switching behavior 有权
标题翻译：用于改进设备切换行为的Cascode方案
公开(公告)号：US08896131B2
公开(公告)日：2014-11-25
申请号：US13020758
申请日：2011-02-03
申请人： Anup Bhalla , Sik Lui , Jun Hu , Fei Wang
发明人： Anup Bhalla , Sik Lui , Jun Hu , Fei Wang
IPC分类号： H01L23/528 , H03K17/10 , H03K17/04 , H01L27/085 , H01L27/06 , H03K17/567 , H03K17/687
CPC分类号： H03K17/6871 , H01L27/0629 , H01L27/085 , H01L2224/73265 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H03K17/0406 , H03K17/102 , H03K17/567 , H03K2017/6875 , H01L2924/00
摘要： A switching device includes a low voltage normally-off transistor and a control circuit built into a common die. The device includes source, gate and drain electrodes for the transistor and one or more auxiliary electrodes. The drain electrode is on one surface of a die on which the transistor is formed, while each of the remaining electrodes is located on an opposite surface. The one or more auxiliary electrodes provide electrical contact to the control circuit, which is electrically connected to one or more of the other electrodes.
摘要翻译：开关器件包括低电压常关晶体管和内置在公共管芯中的控制电路。该器件包括用于晶体管的源极，栅极和漏极以及一个或多个辅助电极。漏电极在其上形成晶体管的管芯的一个表面上，而每个剩余的电极位于相对的表面上。一个或多个辅助电极提供与控制电路的电接触，该电接触电连接到一个或多个其它电极。

48. 发明申请

US20140151790A1 APPROACH TO INTEGRATE SCHOTTKY IN MOSFET 有权
标题翻译：在MOSFET中整合肖特基的方法
公开(公告)号：US20140151790A1
公开(公告)日：2014-06-05
申请号：US13873017
申请日：2013-04-29
申请人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7806 , H01L27/0629 , H01L29/0619 , H01L29/0623 , H01L29/1095 , H01L29/41766 , H01L29/66734 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.
摘要翻译：集成结构结合了场效应晶体管和肖特基二极管。形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。衬底组合物的暴露部分分离身体区域。每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。

49. 发明授权

US08431470B2 Approach to integrate Schottky in MOSFET 有权
标题翻译：将肖特基集成在MOSFET中的方法
公开(公告)号：US08431470B2
公开(公告)日：2013-04-30
申请号：US13079675
申请日：2011-04-04
申请人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
IPC分类号： H01L21/28 , H01L21/02
CPC分类号： H01L29/7806 , H01L27/0629 , H01L29/0619 , H01L29/0623 , H01L29/1095 , H01L29/41766 , H01L29/66734 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.
摘要翻译：集成结构结合了场效应晶体管和肖特基二极管。形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。衬底组合物的暴露部分分离身体区域。每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。

50. 发明申请

US20120248530A1 APPROACH TO INTERGRATE SCHOTTKY IN MOSFET 有权
标题翻译：将肖特考虑在MOSFET中的方法
公开(公告)号：US20120248530A1
公开(公告)日：2012-10-04
申请号：US13079675
申请日：2011-04-04
申请人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
发明人： Sik Lui , Yi Su , Daniel Ng , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/872 , H01L21/8234
CPC分类号： H01L29/7806 , H01L27/0629 , H01L29/0619 , H01L29/0623 , H01L29/1095 , H01L29/41766 , H01L29/66734 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.
摘要翻译：集成结构结合了场效应晶体管和肖特基二极管。形成衬底组合物的沟槽沿其中形成台面的衬底组合物的深度延伸。每个沟槽填充有导电材料，该导电材料通过形成栅极区域的电介质材料与沟槽壁分离。每个台面形状内部的两个第一导电类型体区部分地沉积到基底组合物的深度中。衬底组合物的暴露部分分离身体区域。每个身体区域内的第二导电类型源区域与每个孔的相邻侧和相邻侧相邻。每个孔内的肖特基势垒金属在分离体区的基底组合物的暴露部分的暴露的垂直侧壁的界面处形成肖特基结。

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