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41. 发明申请

US20060022337A1 Hermetic chip in wafer form 审中-公开
标题翻译：晶圆形密封芯片
公开(公告)号：US20060022337A1
公开(公告)日：2006-02-02
申请号：US11237261
申请日：2005-09-27
申请人： Warren Farnworth , Salman Akram , Alan Wood
发明人： Warren Farnworth , Salman Akram , Alan Wood
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L21/56 , H01L23/291 , H01L23/3107 , H01L24/03 , H01L24/48 , H01L2224/04042 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48464 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01031 , H01L2924/01032 , H01L2924/01074 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/10253 , Y10S438/958 , Y10S438/959 , H01L2224/45099 , H01L2924/00 , H01L2224/85399
摘要： A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process for the fully hermetic sealing of both sides and the edges of the semiconductor chip without the use of a separate package.
摘要翻译：一种完全密封的半导体芯片及其制造方法。本发明的半导体芯片通过使用适用于其上的合适的涂层（例如玻璃）在其两侧及其边缘上完全气密密封，以防止半导体芯片的环境攻击。本发明的完全密封的半导体芯片不需要使用用于芯片的气密密封的单独封装，从而减小这种芯片的尺寸。本发明的半导体芯片的制造方法提供了一种使半导体芯片的两面和边缘完全密封的简单方法，而不需要使用单独的封装。

42. 发明授权

US5578526A Method for forming a multi chip module (MCM) 失效
标题翻译：多芯片模块（MCM）的形成方法
公开(公告)号：US5578526A
公开(公告)日：1996-11-26
申请号：US431452
申请日：1995-05-01
申请人： Salman Akram , Warren Farnworth , Alan Wood
发明人： Salman Akram , Warren Farnworth , Alan Wood
IPC分类号： G01R1/04 , G01R31/28 , H01L21/66 , H01L23/13 , H01L23/32 , H01L21/60
CPC分类号： G01R1/04 , G01R31/2863 , H01L22/22 , H01L23/13 , H01L23/32 , H01L2224/16145 , H01L2224/48227 , H01L2924/09701 , H01L2924/10253
摘要： A method for forming a multi chip module for singulated semiconductor dice or dice contained on a wafer is provided. The method includes forming an interconnect adapted to support and establish an electrical connection with the dice. The interconnect includes a substrate formed of a material such as silicon with raised contact members. The raised contact members include projections adapted to penetrate contact locations on the dice (e.g., bond pads) to a limited penetration depth to establish the electrical connection. A conductive layer and conductive traces are formed on the substrate to form an electrical path to the contact members. Programmable links, such as fuses or anti-fuses, can be included in the electrical path for enabling or disabling select dice of the module. A packaged multi chip module assembly can be formed by encapsulation of the dice and substrate in an insulating material or by forming a ceramic base and cover.
摘要翻译：提供一种用于形成包含在晶片上的单片半导体晶片或骰子的多芯片模块的方法。该方法包括形成适于支撑并建立与骰子的电连接的互连。互连包括由诸如具有凸起接触构件的硅的材料形成的衬底。凸起的接触构件包括适于将骰子（例如，接合垫）上的接触位置穿透到有限的穿透深度以建立电连接的突起。导电层和导电迹线形成在衬底上以形成到接触构件的电路径。可编程链路，如保险丝或反熔丝，可以包含在电气路径中，用于启用或禁用模块的选择骰子。封装的多芯片模块组件可以通过将骰子和基板封装在绝缘材料中或通过形成陶瓷基底和盖而形成。

43. 发明申请

US20050230825A1 Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer 失效
公开(公告)号：US20050230825A1
公开(公告)日：2005-10-20
申请号：US11083057
申请日：2005-03-16
申请人： Salman Akram , Alan Wood , Warren Farnworth
发明人： Salman Akram , Alan Wood , Warren Farnworth
IPC分类号： G01R1/04 , H01L21/60 , H01L23/13 , H01L23/48 , H01L23/498 , H05K3/32
CPC分类号： H01L23/13 , G01R1/0466 , G01R1/0483 , H01L23/49827 , H01L2224/05571 , H01L2224/05573 , H01L2224/131 , H01L2224/16237 , H01L2224/8114 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/15174 , H05K3/325 , H05K3/326 , H01L2224/05599
摘要： The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bumps formed thereon, a substrate having a plurality of contact pads distributed thereon and approximately aligned with the plurality of conductive bumps, and an anisotropically conductive layer disposed between and mechanically coupled to the bumped device and to the substrate. The anisotropically conductive layer electrically couples each of the conductive bumps with a corresponding one of the contact pads. In another embodiment, an apparatus for testing a bumped device having a plurality of conductive bumps includes a substrate having a plurality of contact pads distributed thereon and substantially alignable with the plurality of conductive bumps, and an anisotropically conductive layer disposed on the first surface and engageable with the plurality of conductive bumps to electrically couple each of the conductive bumps with a corresponding one of the contact pads. Alternately, the test apparatus may also include an alignment device or a bumped device handler. In another embodiment, a method of testing a bumped device includes engaging a plurality of contact pads with an anisotropically conductive layer, engaging the plurality of conductive bumps with the anisotropically conductive layer substantially opposite from and in approximate alignment with the plurality of contact pads, forming a plurality of conductive paths through the anisotropically conductive layer so that each of the conductive bumps is electrically coupled to one of the contact pads, and applying test signals through at least some of the contact pads and the conductive paths to at least some of the conductive bumps.

44. 发明申请

US20060017451A1 Substrates including alignment fences 审中-公开
标题翻译：基材包括对准栅栏
公开(公告)号：US20060017451A1
公开(公告)日：2006-01-26
申请号：US11233721
申请日：2005-09-23
申请人： Salman Akram , Alan Wood , Warren Farnworth
发明人： Salman Akram , Alan Wood , Warren Farnworth
IPC分类号： G01R31/02
CPC分类号： H05K7/1061 , B33Y10/00 , B33Y30/00 , B33Y80/00 , G01R1/0408 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/07378 , G01R3/00 , H01L23/32 , H01L23/49827 , H01L2224/16111 , H01L2224/16237 , H01L2224/8114 , H01L2224/81385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01049 , H01L2924/01082 , H01L2924/12042 , H01L2924/12044 , H01L2924/15787 , H01L2924/351 , H05K1/112 , H05K1/141 , H05K3/3436 , H05K2201/049 , H05K2201/09472 , H05K2201/10378 , H05K2201/10734 , H05K2201/2018 , H05K2203/167 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A substrate includes a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, therewith. The fence may include a plurality of adjacent, mutually adhered regions, which may comprise layers. One or more laterally recessed regions may be located at one or more corners of a receptacle formed by the fence to facilitate rough alignment of a semiconductor device with the substrate. The receptacle of the fence may include edges that are configured to progressively align a semiconductor device with the substrate.
摘要翻译：衬底包括接收和对准诸如倒装芯片型半导体器件的半导体器件的栅栏。栅栏可以包括多个相邻的相互粘合的区域，其可以包括层。一个或多个横向凹陷区域可以位于由栅栏形成的容器的一个或多个拐角处，以便半导体器件与衬底的粗略对准。栅栏的插座可以包括被配置为使半导体器件与衬底逐渐对准的边缘。

45. 发明申请

US20080020505A1 PACKAGED MICROELECTRONIC IMAGERS AND METHODS OF PACKAGING MICROELECTRONIC IMAGERS 有权
标题翻译：包装微电子图像和包装微电子图像的方法
公开(公告)号：US20080020505A1
公开(公告)日：2008-01-24
申请号：US11863087
申请日：2007-09-27
申请人： Salman Akram , Charles Watkins , Kyle Kirby , Alan Wood , Wiliam Hiatt
发明人： Salman Akram , Charles Watkins , Kyle Kirby , Alan Wood , Wiliam Hiatt
IPC分类号： H01L21/00
CPC分类号： H01L27/146 , H01L21/76898 , H01L27/14618 , H01L27/148 , H01L31/02016 , H01L2224/48227 , H01L2924/01046 , H01L2924/01066 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/00
摘要： Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad.
摘要翻译：本文公开了微电子成像器，用于封装微电子成像器的方法，以及用于在微电子成像器中形成导电晶片间互连的方法。在一个实施例中，微电子成像管芯可以包括微电子衬底，集成电路和电耦合到集成电路的图像传感器。接合焊盘由衬底承载并电耦合到集成电路。导电晶片互连延伸穿过衬底并与接合焊盘接触。互连可以包括完全延伸穿过衬底和接合焊盘的通道，沉积到通道中并与衬底接触的电介质衬垫，沉积在电介质衬垫的至少一部分上的第一和第二导电层以及导电在第二导电层的至少一部分上沉积到通道中并且电耦合到接合焊盘的填充材料。

46. 发明申请

US20060043509A1 Packaged microelectronic imaging devices and methods of packaging microelectronic imaging devices 有权
公开(公告)号：US20060043509A1
公开(公告)日：2006-03-02
申请号：US10925502
申请日：2004-08-24
申请人： Charles Watkins , David Hembree , Peter Benson , Salman Akram
发明人： Charles Watkins , David Hembree , Peter Benson , Salman Akram
IPC分类号： H01L21/00 , H01L27/14 , H01L31/0232
CPC分类号： H01L27/14625 , H01L24/94 , H01L27/14618 , H01L27/14634 , H01L27/1469 , H01L31/0203 , H01L2224/48091 , H01L2224/48227 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, a microelectronic imaging device includes a microelectronic die having an integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit. The imaging device further includes a cover over the image sensor and a plurality of interconnects in and/or on the cover that are electrically coupled to corresponding bond-pads of the die. The interconnects provide external electrical contacts for the bond-pads of the die. The interconnects can extend through the cover or along a surface of the cover.

47. 发明申请

US20060255418A1 Packaged microelectronic imaging devices and methods of packaging microelectronic imaging device 有权
标题翻译：包装微电子成像装置和包装微电子成像装置的方法
公开(公告)号：US20060255418A1
公开(公告)日：2006-11-16
申请号：US11409058
申请日：2006-04-24
申请人： Charles Watkins , David Hembree , Peter Benson , Salman Akram
发明人： Charles Watkins , David Hembree , Peter Benson , Salman Akram
IPC分类号： H01L31/0232 , H01L31/0203
CPC分类号： H01L27/14625 , H01L24/94 , H01L27/14618 , H01L27/14634 , H01L27/1469 , H01L31/0203 , H01L2224/48091 , H01L2224/48227 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, a microelectronic imaging device includes a microelectronic die having an integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit. The imaging device further includes a cover over the image sensor and a plurality of interconnects in and/or on the cover that are electrically coupled to corresponding bond-pads of the die. The interconnects provide external electrical contacts for the bond-pads of the die. The interconnects can extend through the cover or along a surface of the cover.
摘要翻译：本文公开了微电子成像装置和包装微电子成像装置的方法。在一个实施例中，微电子成像装置包括具有集成电路的微电子管芯，电耦合到集成电路的图像传感器，以及电耦合到集成电路的多个接合焊盘。所述成像装置还包括覆盖在所述图像传感器上的盖和在所述盖中和/或盖上的多个互连件，其电耦合到所述管芯的相应接合焊盘。互连件为模具的焊盘提供外部电触头。互连可以延伸穿过盖或沿着盖的表面。

48. 发明申请

US20070045780A1 Methods of forming blind wafer interconnects, and related structures and assemblies 有权
标题翻译：形成盲晶片互连的方法以及相关的结构和组件
公开(公告)号：US20070045780A1
公开(公告)日：2007-03-01
申请号：US11219315
申请日：2005-09-01
申请人： Salman Akram , Sidney Rigg
发明人： Salman Akram , Sidney Rigg
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05572 , H01L2224/06181 , H01L2224/13022 , H01L2224/13025 , H01L2224/16 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/15311 , H01L2924/00012 , H01L2224/05552
摘要： Methods for forming blind wafer interconnects (BWIs) from the back side of a previously thinned substrate structure such as a semiconductor wafer to the underside of a bond pad on its active surface includes the formation of a blind hole from the back side, application of a passivating layer therein, anisotropically etching to remove passivation material from the blind hole bottom, blanket-depositing at least one conductive layer within the blind hole and over the back side, blanket-depositing a resist in the blind hole and over the back side, planarizing the back side to remove resist and the at least one conductive layer, removing resist from the blind hole, and filling the blind hole with solder or other conductive material or a dielectric material. Variations in the methods include formation of a conductive pad adjacent the back side surface, disposition of a solder ball or other conductive structure on the BWI, or forming an end thereof in the form of an extended slug protruding from the back side (for ball-less attachment) as the outer terminus of the BWI.
摘要翻译：从先前减薄的衬底结构（例如半导体晶片）的背面到其活性表面上的接合焊盘的下侧形成盲晶片互连（BWI）的方法包括从背面形成盲孔，应用钝化层，各向异性蚀刻以从盲孔底部去除钝化材料，在盲孔内和背面上覆盖沉积至少一个导电层，在盲孔中并在背面上覆盖抗蚀剂，平面化背面去除抗蚀剂和至少一个导电层，从盲孔去除抗蚀剂，以及用焊料或其它导电材料或电介质材料填充盲孔。方法的变化包括形成邻近背侧表面的导电垫，在BWI上布置焊球或其它导电结构，或者形成从后侧突出的延伸块状的端部（用于球形 - 较少的附件）作为BWI的外部终端。

49. 发明申请

US20070257373A1 METHODS OF FORMING BLIND WAFER INTERCONNECTS, AND RELATED STRUCTURES AND ASSEMBLIES 有权
标题翻译：形成盲波互连的方法以及相关的结构和组件
公开(公告)号：US20070257373A1
公开(公告)日：2007-11-08
申请号：US11776137
申请日：2007-07-11
申请人： Salman Akram , Sidney Rigg
发明人： Salman Akram , Sidney Rigg
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05572 , H01L2224/06181 , H01L2224/13022 , H01L2224/13025 , H01L2224/16 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/15311 , H01L2924/00012 , H01L2224/05552
摘要： Methods for forming blind wafer interconnects (BWIs) from the back side surface of a substrate structure to the underside of a bond pad on the opposing surface includes the formation of a blind hole from the back side surface, forming a passivating layer therein, removing passivation material from the blind hole bottom, depositing at least one conductive layer within the blind hole, and filling the blind hole with solder or other conductive material or a dielectric material.
摘要翻译：用于从基板结构的背面形成到相对表面上的接合焊盘的下侧的盲晶片互连（BWI）的形成方法包括从背面形成盲孔，在其中形成钝化层，去除钝化从盲孔底部的材料，在盲孔内沉积至少一个导电层，以及用焊料或其它导电材料或电介质材料填充盲孔。

50. 发明申请

US20050269686A1 Method and apparatus for forming modular sockets using flexible interconnects and resulting structures 失效
标题翻译：用于使用柔性互连和结构的结构形成模块插座的方法和装置
公开(公告)号：US20050269686A1
公开(公告)日：2005-12-08
申请号：US11204081
申请日：2005-08-15
申请人： Warren Farnworth , David Corisis , Salman Akram
发明人： Warren Farnworth , David Corisis , Salman Akram
IPC分类号： H01L21/44 , H01L25/065 , H01R12/57 , H01R12/70 , H01R12/72 , H01R12/85 , H05K7/02
CPC分类号： H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06593 , H01L2924/0002 , H01L2924/3011 , H01R12/57 , H01R12/7082 , H01R12/721 , H01R12/856 , H01R13/24 , H01R13/514 , H05K7/023 , Y10T29/49126 , Y10T29/4913 , Y10T29/49147 , Y10T29/49153 , Y10T29/49169 , Y10T29/49204 , Y10T29/49222 , H01L2924/00
摘要： A modular bare die socket assembly is provided for attaching a plurality of miniature semiconductor dice to a substrate. The socket assembly is comprised of a plurality of two-sided plates joined vertically in a horizontal stack, wherein each plate has a die socket for the removable insertion of a bare semiconductor die. A multi-layer interconnect lead tape has a plurality of lithographically formed leads bent on one end to form nodes for attachment to bond pads on the removably inserted semiconductor die, and having opposing ends connectable to the substrate.
摘要翻译：提供了用于将多个微型半导体裸片附接到基板的模块化裸模插座组件。插座组件由在水平叠层中垂直连接的多个双面板组成，其中每个板具有用于可裸插入裸半导体管芯的管芯插座。多层互连引线带具有在一端弯曲的多个光刻形成的引线，以形成用于附接到可移除插入的半导体管芯上的接合焊盘并具有可连接到基板的相对端的节点。

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