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41. 发明授权

US06894341B2 Semiconductor device and manufacturing method 有权
标题翻译：半导体器件及制造方法
公开(公告)号：US06894341B2
公开(公告)日：2005-05-17
申请号：US10326179
申请日：2002-12-23
申请人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
发明人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L31/0328
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.
摘要翻译：半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

42. 发明申请

US20050090052A1 Nonvolatile semiconductor memory device having element isolating region of trench type 有权
公开(公告)号：US20050090052A1
公开(公告)日：2005-04-28
申请号：US10991521
申请日：2004-11-19
申请人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/8238
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： A semiconductor device of a selective gate region having a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating film, and an element isolating region including an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer. The element isolating region isolates an element region and is self-aligned with the first electrode layer, a second insulating film is formed on the first electrode layer and the element isolating region, and an open portion exposes a surface of the first electrode layer and is formed in the second insulating film. A second electrode layer is formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electrically connected to the first electrode layer via the open portion.

43. 发明申请

US20050056895A1 Non-volatile semiconductor memory device and manufacturing method thereof 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20050056895A1
公开(公告)日：2005-03-17
申请号：US10956109
申请日：2004-10-04
申请人： Kazuhiro Shimizu , Yuji Takeuchi
发明人： Kazuhiro Shimizu , Yuji Takeuchi
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A non-volatile semiconductor memory device with a small variation in capacitance-coupling to the stacked gate for memory miniaturization. The device has a memory cell array in which memory cells are arranged in array. Each cell has a first gate and a second gate on a semiconductor substrate. The first gate is formed, via a first gate insulating film, on each of device forming regions isolated by device-isolating insulating films. The second gate is formed on the first gate via a second gate insulating film. The first gate is patterned so that its portion is overlapped on the isolation insulating film from the device forming region. A protective insulating film is provided on the isolation film between the device forming regions and in the vicinity of the first gate. A charge-storage layer of each memory cell has at least two stacked conductive layers with a small isolation width at a low aspect ratio for burying isolation insulating films for high density, to easily fabricate in low cost. The side face of the lowest conductive layer meets the side portion of the isolation region. The highest conductive layer has the same width as or is wider than the lowest conductive layer. The first conductive layer is thin for decrease in aspect ratio for burying the insulating film. The second conductive layer has a specific thickness for attaining a desired capacitance between it and the control gate. The highest layer may be formed in self-alignment with the isolation region and stretched out by isotropic-etching.
摘要翻译：一种与用于存储器小型化的堆叠栅极的电容耦合变化小的非易失性半导体存储器件。该器件具有存储单元阵列，其中存储单元被排列成阵列。每个单元在半导体衬底上具有第一栅极和第二栅极。第一栅极通过第一栅极绝缘膜在通过器件隔离绝缘膜隔离的器件形成区域中形成。第二栅极通过第二栅极绝缘膜形成在第一栅极上。第一栅极被图案化，使得其部分与器件形成区域重叠在隔离绝缘膜上。保护绝缘膜设置在器件形成区域之间和第一栅极附近的隔离膜上。每个存储单元的电荷存储层具有至少两个堆叠的导电层，在低纵横比下具有小的隔离宽度，用于埋入用于高密度的隔离绝缘膜，以便以低成本容易地制造。最低导电层的侧面与隔离区域的侧面相交。最高的导电层具有与最低导电层相同的宽度或比其更宽的导电层。第一导电层对于掩埋绝缘膜的纵横比降低是薄的。第二导电层具有用于在其与控制栅之间获得所需电容的特定厚度。最高层可以与隔离区自对准形成并通过各向同性蚀刻拉伸。

44. 发明授权

US06835978B2 Nonvolatile semiconductor memory device having element isolating region of trench type 有权
标题翻译：具有沟槽型元件隔离区域的非易失性半导体存储器件
公开(公告)号：US06835978B2
公开(公告)日：2004-12-28
申请号：US09956986
申请日：2001-09-21
申请人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu Matsui , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： A semiconductor device of a selective gate region having a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, and an element isolating region including an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer. The element isolating region isolates an element region and is self-aligned with the first electrode layer, a second insulating film is formed on the first electrode layer and the element isolating region, and an open portion exposes a surface of the first electrode layer and is formed in the second insulating film. A second electrode layer is formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electrically connected to the first electrode layer via the open portion.
摘要翻译：具有半导体层的选择栅极区域的半导体器件，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，以及包括元件隔离绝缘膜的元件隔离区域，所述元件隔离绝缘膜形成为延伸穿过第一电极层和第一绝缘膜到达半导体层的内部区域。元件隔离区域隔离元件区域并且与第一电极层自对准，第二绝缘膜形成在第一电极层和元件隔离区域上，开放部分露出第一电极层的表面，并且是形成在第二绝缘膜中。第二电极层形成在第二绝缘膜和第一电极层的暴露表面上，第二电极层经由开口部分电连接到第一电极层。

45. 发明授权

US06806525B2 Semiconductor device and operation method thereof 失效
标题翻译：半导体装置及其动作方法
公开(公告)号：US06806525B2
公开(公告)日：2004-10-19
申请号：US10278854
申请日：2002-10-24
申请人： Yuji Takeuchi , Riichiro Shirota
发明人： Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L27108
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/3454 , H01L27/115
摘要： A semiconductor device with a non-volatile memory, having: first to fourth memory cells arranged in a first direction; a first bit line extending over the first memory cell in a second direction and connected to the second memory cell; a second bit line extending over the second memory cell in the second direction and connected to the first memory cell; a third bit line extending over the third memory cell in the second direction and connected to the third memory cell; and a fourth bit line extending over the fourth memory cell in the second direction and connected to the fourth memory cell.
摘要翻译：一种具有非易失性存储器的半导体器件，具有：沿第一方向布置的第一至第四存储器单元; 第一位线，沿着第二方向在第一存储单元上延伸并连接到第二存储器单元; 第二位线在第二方向上延伸到第二存储器单元上并连接到第一存储器单元; 第三位线，沿着第二方向在第三存储单元上延伸并连接到第三存储器单元; 以及在所述第四方向上延伸到所述第四存储器单元上并连接到所述第四存储器单元的第四位线。

46. 发明授权

US06512253B2 Nonvolatile semiconductor memory 失效
公开(公告)号：US06512253B2
公开(公告)日：2003-01-28
申请号：US09976317
申请日：2001-10-15
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： H01L2710
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has a plurality of contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

47. 发明授权

US06353242B1 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US06353242B1
公开(公告)日：2002-03-05
申请号：US09274481
申请日：1999-03-23
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： G11C1604
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has a plurality of contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
摘要翻译：选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。第一级导电层具有多个接触区域。第二级导电层的部分被去除，位于接触区域上方。在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

48. 发明授权

US6160297A Semiconductor memory device having a first source line arranged between a memory cell string and bit lines in the direction crossing the bit lines and a second source line arranged in parallel to the bit lines 失效
标题翻译：半导体存储器件具有布置在存储单元串和与位线交叉的方向上的位线之间的第一源极线和与位线并联布置的第二源极线
公开(公告)号：US6160297A
公开(公告)日：2000-12-12
申请号：US17803
申请日：1998-02-03
申请人： Kazuhiro Shimizu , Hiroshi Watanabe , Yuji Takeuchi , Seiichi Aritome , Toshiharu Watanabe
发明人： Kazuhiro Shimizu , Hiroshi Watanabe , Yuji Takeuchi , Seiichi Aritome , Toshiharu Watanabe
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94
CPC分类号： H01L27/11519 , H01L21/76877 , H01L21/76897 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device comprises select gates and control gates of a plurality of memory cells therebetween so that gate members on upper portions of stacked gates may cross element regions. A metal interconnection is disposed parallel to an upper layer of the element region. A source line SL is arranged at intervals of plural bit lines BL. The source line is led to a source line contact through a conductive member composed of a low-resistance metal in the same manner as a bit line contact.
摘要翻译：半导体器件包括其间的多个存储单元的选择栅极和控制栅极，使得堆叠栅极的上部的栅极元件可以跨元件区域。金属互连平行于元件区域的上层设置。源极线SL以多个位线BL的间隔排列。以与位线接触相同的方式，将源极线通过由低电阻金属构成的导电构件引导到源极线接触。

49. 发明授权

US6068916A Tension member for belt, method of producing the same and belt including the same 失效
标题翻译：带的张紧构件，其制造方法以及包括其的带
公开(公告)号：US6068916A
公开(公告)日：2000-05-30
申请号：US736359
申请日：1996-10-23
申请人： Yuji Takeuchi
发明人： Yuji Takeuchi
IPC分类号： F16G1/08 , F16G5/06 , D02G3/00
CPC分类号： F16G1/08 , F16G5/06 , Y10T428/2933 , Y10T428/2936 , Y10T428/2938 , Y10T428/2964
摘要： A plurality of glass fiber strands are parallel-arranged and primary-twisted into a primary twist yarn. A plurality of the primary twist yarns are parallel-arranged, are dipped in an adhesion treatment liquid containing as a main ingredient a mixture of a precondensate of resorcine formaldehyde and latex, are returned from the liquid and are then subjected to heat treatment. Thereafter, the plurality of primary twist yarns are final-twisted thereby forming a tension member for belt having a large adhesive property between the adjacent primary twist yarns.
摘要翻译：多根玻璃纤维丝线平行排列并初捻成一次捻纱。多个一次加捻纱线平行布置，浸入含有作为主要成分的甲醛和胶乳的预缩合物的混合物的粘合处理液体中，从液体中返回，然后进行热处理。此后，多个一次加捻纱线最终扭曲，从而形成相邻的一次加捻纱线之间具有大的粘合性能的带状张紧部件。

50. 发明授权

US5876297A Tension member for a power transmission belt having a braiding pitch to diameter ratio within a specific range to increase the flex fatigue resistance of the belt 失效
标题翻译：用于具有编织间距直径比在特定范围内的传动带的张紧构件，以增加带的抗挠曲疲劳性
公开(公告)号：US5876297A
公开(公告)日：1999-03-02
申请号：US753500
申请日：1996-11-26
申请人： Yuji Takeuchi
发明人： Yuji Takeuchi
IPC分类号： B29D29/00 , B29K9/00 , B29K105/08 , D07B1/02 , F16G1/28 , F16G1/10
CPC分类号： F16G1/28 , D07B1/025 , D07B2205/205
摘要： A tension member of a power transmission belt is formed of a braided cord composed of four aramid fiber strands having the same yarn number. The yarn number of the aramid fiber strands is 700 denier to 1300 denier. A ratio p/d of a braiding pitch p of the braided cord to a diameter d thereof is 3.7.ltoreq.p/d.ltoreq.5.5. Thereby increasing the flex fatigue resistance of the power transmission belt.
摘要翻译：动力传递带的张力构件由具有相同纱数的四根芳族聚酰胺纤维束构成的编织线构成。芳族聚酰胺纤维束的纱数为700旦至1300旦。编织帘线的编织间距p与其直径d的比p / d为3.7≤p/d≤5.5。从而增加动力传动带的抗弯曲疲劳性能。

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