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41. 发明授权

US09202071B2 Exception handling in a data processing apparatus having a secure domain and a less secure domain 有权
标题翻译：具有安全域和较不安全域的数据处理装置中的异常处理
公开(公告)号：US09202071B2
公开(公告)日：2015-12-01
申请号：US13741709
申请日：2013-01-15
申请人： ARM Limited
发明人： Thomas Christopher Grocutt , Richard Roy Grisenthwaite
IPC分类号： G06F21/00 , G06F21/60 , G06F21/52 , G06F21/74 , G06F9/30
CPC分类号： G06F21/606 , G06F9/3009 , G06F9/30101 , G06F21/52 , G06F21/74 , G06F2209/481 , G06F2221/2105
摘要： A data processing apparatus and method are provided for handling exceptions, including processing circuitry configured to perform data processing operations in response to program code, said circuitry including exception control circuitry. A plurality of registers are provided including a first and second subsets of registers, and a data store. The data store includes a secure region and a less secure region, wherein the secure region is for storing data accessible by the processing circuitry when operating in a secure domain and not accessible by the processing circuitry when operating in a less secure domain. The exception control circuitry performs state saving of data from the first subset of registers before triggering the processing circuitry to perform an exception handling routine corresponding to the exception. Where background processing was performed by the processing circuitry in the secure domain, the exception control circuitry performs additional state saving of the data.
摘要翻译：提供了一种用于处理异常的数据处理装置和方法，包括配置为响应于程序代码执行数据处理操作的处理电路，所述电路包括异常控制电路。提供了多个寄存器，包括第一和第二寄存器子集，以及数据存储器。数据存储器包括安全区域和较不安全的区域，其中安全区域用于存储当在安全域中操作时由处理电路可访问的数据，并且当在较不安全的域中操作时由处理电路不可访问。异常控制电路在触发处理电路之前对寄存器的第一子集进行数据的状态保存，以执行与异常相对应的异常处理程序。在由安全域中的处理电路执行背景处理的情况下，异常控制电路执行数据的附加状态保存。

42. 发明公开

US20240070071A1 CONTEXT INFORMATION TRANSLATION CACHE 审中-公开
公开(公告)号：US20240070071A1
公开(公告)日：2024-02-29
申请号：US18259827
申请日：2021-11-25
申请人： Arm Limited
发明人： Andrew Brookfield Swaine , Richard Roy Grisenthwaite
IPC分类号： G06F12/0811 , G06F12/0837 , G06F12/0875
CPC分类号： G06F12/0811 , G06F12/0837 , G06F12/0875
摘要： A context-information-dependent instruction causes a context-information-dependent operation to be performed based on specified context information indicative of a specified execution context. A context information translation cache 10 stores context information translation entries each specifying untranslated context information and translated context information. Lookup circuitry 14 performs a lookup of the context information translation cache based on the specified context information, to identify whether the context information translation cache includes a matching context information translation entry which is valid and which specifies untranslated context information corresponding to the specified context information. When the matching context information translation entry is identified, the context-information-dependent operation is performed based on the translated context information specified by the matching context information translation entry.

43. 发明授权

US11669467B2 Memory access instructions 有权
公开(公告)号：US11669467B2
公开(公告)日：2023-06-06
申请号：US15768909
申请日：2016-09-06
申请人： ARM LIMITED
发明人： Jason Parker , Richard Roy Grisenthwaite
IPC分类号： G06F12/14 , G06F9/30 , G06F21/60 , G06F21/79 , G06F12/08 , G06F9/54 , G06F12/084
CPC分类号： G06F12/1441 , G06F9/30043 , G06F9/30145 , G06F9/544 , G06F12/084 , G06F12/14 , G06F12/1408 , G06F12/1475 , G06F12/1491 , G06F21/60 , G06F21/79 , G06F2212/1052
摘要： Processing circuitry performs processing operations specified by program instructions, and a decoder decodes memory access instructions to generate control signals to control the processing circuitry to perform memory access operations. The memory access instructions have respective encodings specifying protected memory access instructions corresponding to protected memory access operations and less-protected memory access instructions corresponding to less-protected memory access operations. The less-protected memory access operations are associated with less restrictive memory access conditions than the protected memory access operations.

44. 发明授权

US11615032B2 Address translation data invalidation 有权
公开(公告)号：US11615032B2
公开(公告)日：2023-03-28
申请号：US16625102
申请日：2018-06-01
申请人： ARM LIMITED
发明人： Matthew James Horsnell , Grigorios Magklis , Richard Roy Grisenthwaite
IPC分类号： G06F3/06 , G06F12/1027 , G06F9/46 , G06F9/54 , G06F12/0873
摘要： A data processing system (2) including one or more transaction buffers (16, 18, 20) storing address translation data executes translation buffer invalidation instructions TLBI within respective address translation contexts VMID, ASID, X. Translation buffer invalidation signals generated as a consequence of execution of the translation buffer invalidation instructions are broadcast to respective translation buffers and include signals which specify the address translation context of the translation buffer invalidation instruction that was executed. This address translation context specified within the translation buffer invalidation signals is used to gate whether or not those translation buffer invalidation signals when received by translation buffers which are potential targets for the invalidation are or are not flushed. The address translation context data provided within the translation buffer invalidation signals may also be used to control whether or not local memory transactions for a local transactional memory access are or are not aborted upon receipt of the translation buffer invalidation signals.

45. 发明授权

US11579873B2 Handling load-exclusive instructions in apparatus having support for transactional memory 有权
公开(公告)号：US11579873B2
公开(公告)日：2023-02-14
申请号：US17255001
申请日：2019-05-09
申请人： Arm Limited
发明人： Matthew James Horsnell , Grigorios Magklis , Richard Roy Grisenthwaite , Nathan Yong Seng Chong
IPC分类号： G06F9/30 , G06F9/38
摘要： An apparatus is described with support for transactional memory and load/store-exclusive instructions using an exclusive monitor indication to track exclusive access to a given address. In response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, any exclusive monitor indication previously set for the load target address is cleared. In response to a load-exclusive instruction, an abort is triggered for a transaction for which the given address is specified as one of its working set of addresses. This helps to maintain mutual exclusion between transactional and non-transactional threads even if there is load speculation in the non-transactional thread.

46. 发明授权

US11461243B2 Speculative cache storage region 有权
公开(公告)号：US11461243B2
公开(公告)日：2022-10-04
申请号：US16959280
申请日：2018-08-30
申请人： Arm Limited
发明人： Richard Roy Grisenthwaite
IPC分类号： G06F12/00 , G06F12/126 , G06F9/30 , G06F12/0811 , G06F12/0846 , G06F12/0871 , G06F12/0875 , G06F12/128
摘要： An apparatus (2) comprises processing circuitry (4) to perform speculative execution of instructions; a main cache storage region (30); a speculative cache storage region (32); and cache control circuitry (34) to allocate an entry, for which allocation is caused by a speculative memory access triggered by the processing circuitry, to the speculative cache storage region instead of the main cache storage region while the speculative memory access remains speculative. This can help protect against potential security attacks which exploit cache timing side-channels to gain information about allocations into the cache caused by speculative memory accesses.

47. 发明授权

US11379233B2 Apparatus and data processing method for transactional memory 有权
公开(公告)号：US11379233B2
公开(公告)日：2022-07-05
申请号：US17269216
申请日：2019-10-17
申请人： Arm Limited
发明人： Matthew James Horsnell , Richard Roy Grisenthwaite
IPC分类号： G06F9/30 , G06F9/46 , G06F9/38
摘要： In an apparatus with transactional memory support circuitry, for a first type of transaction started using a first type of transaction start instruction, commitment of results of instructions executed speculatively following the first type of transaction start instruction are prevented until a transaction end instruction is reached. An abort is triggered when a conflict is detected between an address of a memory access from another thread and the addresses tracked for the transaction. For a second type of transaction started using a second type of transaction start instruction, an address of the read operation is marked as trackable whilst an address of a write operation is omitted from being marked as trackable. This allows an apparatus that supports transactional memory to also be used for multi-word address watching.

48. 发明授权

US10949292B1 Memory interface having data signal path and tag signal path 有权
公开(公告)号：US10949292B1
公开(公告)日：2021-03-16
申请号：US16594223
申请日：2019-10-07
申请人： Arm Limited
发明人： Bruce James Mathewson , Phanindra Kumar Mannava , Michael Andrew Campbell , Alexander Alfred Hornung , Alex James Waugh , Klas Magnus Bruce , Richard Roy Grisenthwaite
IPC分类号： G06F11/20 , G11C29/08 , G06F11/10 , G11C29/18 , G06F11/30
摘要： A requester issues a request specifying a target address indicating an addressed location in a memory system. A completer responds to the request. Tag error checking circuitry performs a tag error checking operation when the request issued by the requester is a tag-error-checking request specifying an address tag. The tag error checking operation comprises determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request. The requester and the completer communicate via a memory interface having at least one data signal path to exchange read data or write data between the requester and the completer; and at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the requester and the completer.

49. 发明授权

US10802729B2 Apparatus and method for sharing pages including enforcing ownership rights independently of privilege level 有权
公开(公告)号：US10802729B2
公开(公告)日：2020-10-13
申请号：US15574549
申请日：2016-04-26
申请人： ARM LIMITED
发明人： Jason Parker , Richard Roy Grisenthwaite , Andrew Christopher Rose
IPC分类号： G06F3/06 , G06F9/455 , G06F12/1009 , G06F12/14
摘要： A data processing system comprises ownership circuitry to enforce ownership rights of memory regions within a physical memory address space. A given memory region has a given owning process specified from among a plurality of processes and independently of privilege level. The given owning process has rights to control access to the given memory region. The given owning process designates the given memory region as one of: private to the given owning process and shared between the given owning process and at least one further source of memory access requests. A given owning process may deny access to the given memory region to a process having a greater level of privilege than the given owning process. Data stored within the given memory region may be destructively overwritten, and completion of the overwriting may be tracked by overwrite tracking hardware to ensure completion of the overwriting before the new owner obtains rights to control access.

50. 发明授权

US10795675B2 Determine whether to fuse move prefix instruction and immediately following instruction independently of detecting identical destination registers 有权
公开(公告)号：US10795675B2
公开(公告)日：2020-10-06
申请号：US15761476
申请日：2016-09-14
申请人： ARM LIMITED
发明人： Richard Roy Grisenthwaite , Nigel John Stephens
IPC分类号： G06F9/30 , G06F9/38
摘要： An apparatus 2 has instruction fusing circuitry 50 for fusing two or more instructions fetched from a data store to generate a fused instruction to be processed by processing circuitry 14. A move prefix instruction is provided which indicates to the instruction fusing circuitry 50 that the move prefix instruction can be fused with an immediately following data processing instruction without needing to compare registers specified by the move prefix instruction and the immediately following instruction. This enables the instruction fusing circuitry 50 to be implemented with reduced hardware and energy cost.

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