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41. 发明申请

US20090130826A1 Method of Forming a Semiconductor Device Having a Strained Silicon Layer on a Silicon-Germanium Layer 审中-公开
标题翻译：在硅锗层上形成具有应变硅层的半导体器件的方法
公开(公告)号：US20090130826A1
公开(公告)日：2009-05-21
申请号：US12330796
申请日：2008-12-09
申请人： Young-Pil Kim , Sun-Ghil Lee , Yu-Gyun Shin , Jong-Wook Lee , In-Soo Jung
发明人： Young-Pil Kim , Sun-Ghil Lee , Yu-Gyun Shin , Jong-Wook Lee , In-Soo Jung
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L29/1054 , H01L29/66651 , H01L29/78
摘要： A method of forming a semiconductor device having a strained silicon (Si) layer on a silicon germanium (SiGe) layer is provided. The method includes preparing a silicon substrate. A SiGe layer is formed on the silicon substrate. At least a part of the SiGe layer has a first dislocation density. A strained Si layer having a second dislocation density lower than the first dislocation density is formed on the SiGe layer.
摘要翻译：提供了在硅锗（SiGe）层上形成具有应变硅（Si）层的半导体器件的方法。该方法包括制备硅衬底。在硅衬底上形成SiGe层。至少一部分SiGe层具有第一位错密度。在SiGe层上形成具有低于第一位错密度的第二位错密度的应变Si层。

42. 发明申请

US20060292783A1 CMOS transistor and method of manufacturing the same 有权
标题翻译： CMOS晶体管及其制造方法
公开(公告)号：US20060292783A1
公开(公告)日：2006-12-28
申请号：US11363176
申请日：2006-02-28
申请人： Young-eun Lee , Seong-ghil Lee , Yu-gyun Shin , Jong-wook Lee , Young-pil Kim
发明人： Young-eun Lee , Seong-ghil Lee , Yu-gyun Shin , Jong-wook Lee , Young-pil Kim
IPC分类号： H01L21/8238 , H01L29/80
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a source/drain region formed in relation to an epitaxial layer formed in a recess region.
摘要翻译：公开了一种CMOS晶体管结构及相关的制造方法，其中第一导电型MOS晶体管包括增强器，第二导电类型MOS晶体管包括由与增强器相同的材料形成的第二间隔物。第二导电型MOS晶体管还包括相对于形成在凹陷区域中的外延层形成的源极/漏极区域。

43. 发明申请

US20060128140A1 Method of forming a contact hole in a semiconductor device 失效
标题翻译：在半导体器件中形成接触孔的方法
公开(公告)号：US20060128140A1
公开(公告)日：2006-06-15
申请号：US11289938
申请日：2005-11-29
申请人： Young-Pil Kim
发明人： Young-Pil Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/31144
摘要： An exemplary method of forming a contact hole in a semiconductor device includes: forming a first insulation layer on a lower substrate; forming a first conductive layer on the first insulation layer; forming a second insulation layer on the first insulation layer and the first conductive layer; forming a second conductive layer on the second insulation layer; forming a third insulation layer on the second insulation layer and the second conductive layer; patterning a resist on the third insulation layer using an exposure mask of which transmittance is different at a region over the first conductive layer and at a region over the second conductive layer; and forming a first contact hole and a second contact hole by etching the resist and the third insulation layer such that the first conductive layer and the second conductive layer are exposed.
摘要翻译：在半导体器件中形成接触孔的示例性方法包括：在下基板上形成第一绝缘层; 在所述第一绝缘层上形成第一导电层; 在所述第一绝缘层和所述第一导电层上形成第二绝缘层; 在所述第二绝缘层上形成第二导电层; 在所述第二绝缘层和所述第二导电层上形成第三绝缘层; 使用在第一导电层上方的区域和第二导电层上的区域的透射率不同的曝光掩模在第三绝缘层上构图抗蚀剂; 以及通过蚀刻抗蚀剂和第三绝缘层形成第一接触孔和第二接触孔，使得第一导电层和第二导电层露出。

44. 发明授权

US06897109B2 Methods of manufacturing integrated circuit devices having contact holes using multiple insulating layers 失效
标题翻译：制造具有使用多个绝缘层的接触孔的集成电路器件的方法
公开(公告)号：US06897109B2
公开(公告)日：2005-05-24
申请号：US10864277
申请日：2004-06-09
申请人： Beom-Jun Jin , Young-Pil Kim
发明人： Beom-Jun Jin , Young-Pil Kim
IPC分类号： H01L21/28 , H01L21/02 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10855 , H01L21/76802 , H01L21/76831 , H01L21/76885 , H01L21/76895 , H01L21/76897 , H01L27/10814 , H01L27/10885 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides methods of forming contact holes and integrated circuit devices having the same. A conductive plug is formed on a substrate. A first insulating layer is formed on the conductive plug and a second insulating layer is formed on the first insulating layer. The second insulating layer is etched to expose at least a portion of the first insulating layer and the first insulating layer is etched to expose at least a portion of the conductive plug.
摘要翻译：本发明提供形成接触孔的方法和具有该接触孔的集成电路器件。在基板上形成导电塞。在导电插塞上形成第一绝缘层，在第一绝缘层上形成第二绝缘层。蚀刻第二绝缘层以暴露第一绝缘层的至少一部分，并且蚀刻第一绝缘层以暴露至少一部分导电插塞。

45. 发明授权

US06462141B1 Diene copolymer substituted by alkoxy silane, and organic and inorganic hybrid composition comprising the same 失效
标题翻译：由烷氧基硅烷取代的二烯共聚物和包含它们的有机和无机杂化组合物
公开(公告)号：US06462141B1
公开(公告)日：2002-10-08
申请号：US09460643
申请日：1999-12-15
申请人： Eun-Kyoung Kim , Hyung-Suk Cho , Young-Pil Kim
发明人： Eun-Kyoung Kim , Hyung-Suk Cho , Young-Pil Kim
IPC分类号： C08F800
CPC分类号： C08F8/42 , C08C19/25
摘要： The present invention relates to alkoxysilane-substituted diene copolymers, organic and inorganic hybrid complex compositions comprising the same and a process for the preparation of the same. The alkoxysilane-substituted diene copolymers are prepared by reacting a diene copolymer substituted by epoxy or hydroxy groups with a silane compound. Thus prepared alkoxysilane-substituted diene copolymer is characterized by the facts that it is in organic solvents and it is capable of being cured at low temperatures. The present invention also relates to a composition prepared by mixing the said copolymer with inorganic fillers and/or coupling agents. The copolymer of the formula (1) has high reactivity with coupling agents since it possesses reactive silane groups and thus provides the diene polymer composition as having improved compatibility with inorganic fillers. In addition, when the copolymer of the formula (1) is added to a sol-gel reactant, a substitution reaction proceeds smoothly even under mild reaction conditions and thus it is possible to introduce the third functional group to copolymer blocks.
摘要翻译：本发明涉及烷氧基硅烷取代的二烯共聚物，包含它们的有机和无机杂化复合组合物及其制备方法。烷氧基硅烷取代的二烯共聚物通过使被环氧基或羟基取代的二烯共聚物与硅烷化合物反应来制备。由此制备的烷氧基硅烷取代的二烯共聚物的特征在于它在有机溶剂中并且能够在低温下固化。本发明还涉及通过将所述共聚物与无机填料和/或偶联剂混合而制备的组合物。式（1）的共聚物与偶联剂具有高反应性，因为它具有反应性硅烷基团，因此提供二烯聚合物组合物具有改善的与无机填料的相容性。此外，当将式（1）的共聚物加入到溶胶 - 凝胶反应物中时，即使在温和的反应条件下，取代反应也能顺利进行，因此可以将第三官能团引入共聚物嵌段。

46. 发明授权

US6043537A Embedded memory logic device using self-aligned silicide and manufacturing method therefor 失效
标题翻译：使用自对准硅化物的嵌入式存储器逻辑器件及其制造方法
公开(公告)号：US6043537A
公开(公告)日：2000-03-28
申请号：US016092
申请日：1998-01-30
申请人： In-kyun Jun , Young-pil Kim , Hyung-moo Park , Myeon-koo Kang
发明人： In-kyun Jun , Young-pil Kim , Hyung-moo Park , Myeon-koo Kang
IPC分类号： H01L27/10 , H01L21/8229 , H01L21/8242 , H01L21/8244 , H01L27/01
CPC分类号： H01L27/10894 , H01L27/11 , H01L27/10873 , H01L27/10888
摘要： The operating speed and refresh characteristics of an embedded memory logic device having a silicide layer is improved by excluding the silicide from the source/drain region between access gates and pass gates in a cell array region, thereby reducing leakage current. The source/drain region between access gates and pass gates are also lightly doped to further reduce leakage current. An embedded memory logic device fabricated in accordance with the present invention includes a semiconductor substrate including first and second regions. A first gate electrode is formed over the first region. A first drain region doped with a first impurity is formed in the semiconductor substrate on one side of the first gate electrode, and a first source doped with a second impurity is formed in the semiconductor substrate on the other side of the first gate electrode. A second gate electrode is formed on a second region of the semiconductor substrate, and second source/drain regions doped with a third impurity are formed in the semiconductor substrate on both sides of the second gate electrode. Also, a third gate electrode is formed on the second region of the semiconductor substrate, and third source/drain regions doped with a fourth impurity are formed on both sides of the third gate electrode. Metal silicide layers are formed on the first through third gate electrodes, on the first drain region, and on the second and third source/drain regions.
摘要翻译：具有硅化物层的嵌入式存储器逻辑器件的工作速度和刷新特性通过从栅极阵列区域中的栅极和栅极之间的源极/漏极区域排除硅化物来改善，从而减少漏电流。存取栅极和栅极之间的源极/漏极区域也被轻掺杂，以进一步减少漏电流。根据本发明制造的嵌入式存储器逻辑器件包括包括第一和第二区域的半导体衬底。在第一区域上形成第一栅电极。掺杂有第一杂质的第一漏区形成在第一栅电极的一侧的半导体衬底中，并且在第一栅电极的另一侧上的半导体衬底中形成掺杂有第二杂质的第一源。第二栅电极形成在半导体衬底的第二区域上，并且掺杂有第三杂质的第二源极/漏极区域形成在第二栅电极两侧的半导体衬底中。此外，在半导体衬底的第二区域上形成第三栅电极，在第三栅电极的两侧形成掺杂有第四杂质的第三源/漏区。金属硅化物层形成在第一至第三栅极电极，第一漏极区域以及第二和第三源极/漏极区域上。

47. 发明授权

US5714401A Semiconductor device capacitor manufactured by forming stack with multiple material layers without conductive layer therebetween 失效
标题翻译：通过形成具有多个材料层的叠层而不具有导电层的半导体器件电容器
公开(公告)号：US5714401A
公开(公告)日：1998-02-03
申请号：US521985
申请日：1995-08-31
申请人： Young-pil Kim , Jong-bok Kim , Won-sik Lee , Yong-hee Lee
发明人： Young-pil Kim , Jong-bok Kim , Won-sik Lee , Yong-hee Lee
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method is provided for manufacturing a capacitor of a semiconductor device. First, an insulating layer, an etching barrier layer, a first material layer and a second material layer are sequentially stacked on a semiconductor substrate on which a field oxide layer and a gate electrode are formed, and predetermined portions of the stacked layers are sequentially etched to form a contact hole exposing the substrate. Then, a first conductive layer is formed on thge whole surface of the resultant structure having the contact hole. Subsequently, a storage electrode pattern is formed by patterning the first conductive layer and etching the second material layer. Then, a second conductive layer is formed on the whole surface of the resultant structure so as to cover the storage electrode pattern and the first material layer. Thereafter, the second conductive layer is etched to expose the upper surface of the storage electrode pattern. Therefore, the capacitor manufacturing process, particularly, the etching process, is simplified, and can be applied to a capacitor having a COB structure.
摘要翻译：提供一种用于制造半导体器件的电容器的方法。首先，将绝缘层，蚀刻阻挡层，第一材料层和第二材料层依次层叠在其上形成有场氧化物层和栅电极的半导体基板上，并且层叠的预定部分被依次蚀刻以形成露出衬底的接触孔。然后，在具有接触孔的所得结构的整个表面上形成第一导电层。随后，通过图案化第一导电层并蚀刻第二材料层来形成存储电极图案。然后，在所得结构的整个表面上形成第二导电层，以覆盖存储电极图案和第一材料层。此后，蚀刻第二导电层以暴露存储电极图案的上表面。因此，电容器制造工艺，特别是蚀刻工艺被简化，并且可以应用于具有COB结构的电容器。

48. 发明授权

US5422295A Method for forming a semiconductor memory device having a vertical multi-layered storage electrode 失效
标题翻译：用于形成具有垂直多层存储电极的半导体存储器件的方法
公开(公告)号：US5422295A
公开(公告)日：1995-06-06
申请号：US164671
申请日：1993-12-10
申请人： Young-jae Choi , Tae-young Chung , Jong-woo Park , Young-pil Kim
发明人： Young-jae Choi , Tae-young Chung , Jong-woo Park , Young-pil Kim
IPC分类号： H01L27/04 , H01L21/02 , H01L21/265 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L28/86 , H01L21/26533 , H01L28/87 , H01L28/88
摘要： A manufacturing method for a semiconductor memory device including a capacitor having a double fin-shaped structure is provided, wherein a storage electrode is formed by applying a thick planar material capable of being wet-etched between the double fins consisting of conductive layers. The storage electrode is formed by forming a thin, high temperature oxide film having an etching rate which is great. Thus, the resulting memory cell's topography is improved and damage to the storage electrode is decreased.
摘要翻译：提供了一种包括具有双鳍状结构的电容器的半导体存储器件的制造方法，其中通过在由导电层组成的双翅片之间施加能够被湿蚀刻的厚平面材料形成存储电极。存储电极通过形成蚀刻速率大的薄的高温氧化膜形成。因此，所得到的存储单元的形貌得到改善，并且对存储电极的损坏降低。

49. 发明授权

US08853010B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08853010B2
公开(公告)日：2014-10-07
申请号：US13368584
申请日：2012-02-08
申请人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
发明人： Heung-Kyu Park , Woo-Bin Song , Nam-Kyu Kim , Su-Jin Jung , Byeong-Chan Lee , Young-Pil Kim , Sun-Ghil Lee
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336 , H01L21/337 , H01L21/338 , H01L21/339 , H01L29/165 , H01L29/78 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/1608 , H01L29/165 , H01L29/66545 , H01L29/66621 , H01L29/66651 , H01L29/78
摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.
摘要翻译：半导体器件包括衬底和在衬底上彼此间隔开的第一和第二应力产生外延区域。沟道区位于衬底上并位于第一和第二应力产生外延区之间。栅电极在沟道区上。沟道区域是外延层，并且第一和第二应力产生外延区域对沟道区域施加应力。

50. 发明授权

US08508980B2 Polarity dependent switch for resistive sense memory 有权
标题翻译：用于电阻式读出存储器的极性依赖开关
公开(公告)号：US08508980B2
公开(公告)日：2013-08-13
申请号：US13278334
申请日：2011-10-21
申请人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
发明人： Chulmin Jung , Maroun Georges Khoury , Yong Lu , Young Pil Kim
IPC分类号： H01L29/78 , H01L45/00 , G11C11/00
CPC分类号： G11C11/16 , G11C11/1659 , H01L27/228 , H01L29/1083
摘要： A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically is connected to the bit contact. The source contact is more heavily implanted with dopant material then the bit contact.
摘要翻译：存储单元包括电阻读出存储单元，配置为在通过电阻读出存储单元的电流和与电阻读出存储单元电连接的半导体晶体管时，在高电阻状态和低电阻状态之间切换。半导体晶体管包括形成在基板上的栅极元件。半导体晶体管包括源极触点和位触点。门元件电连接源触点和触点触点。电阻读出存储单元电连接到位触点。源触点被更多地注入掺杂剂材料，然后进行位接触。

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