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41. 发明授权

US08972697B2 Gather using index array and finite state machine 有权
标题翻译：收集使用索引数组和有限状态机
公开(公告)号：US08972697B2
公开(公告)日：2015-03-03
申请号：US13487184
申请日：2012-06-02
申请人： Zeev Sperber , Robert Valentine , Guy Patkin , Stanislav Shwartsman , Shlomo Raikin , Igor Yanover , Gal Ofir
发明人： Zeev Sperber , Robert Valentine , Guy Patkin , Stanislav Shwartsman , Shlomo Raikin , Igor Yanover , Gal Ofir
IPC分类号： G06F12/02
CPC分类号： G06F15/8007 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345 , G06F9/3887
摘要： Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.
摘要翻译：公开了使用索引阵列和有限状态机进行散射/收集操作的方法和装置。设备的实施例可以包括：解码逻辑以解码分散/收集指令并生成一组微操作，以及索引阵列以保存一组索引和相应的一组掩码元素。有限状态机有助于收集操作。地址生成逻辑从针对具有第一值的对应掩模元素中的至少每一个的索引集合的索引生成地址。如果mask元素具有第一个值，则访问地址以加载相应的数据元素。根据相应的注册位置的索引，将数据元素写入到目的地向量寄存器的寄存器位置。响应于其相应负载的完成，对应的屏蔽元件的值从第一值改变为第二值。

42. 发明申请

US20150006805A1 HYBRID MULTI-LEVEL MEMORY ARCHITECTURE 有权
标题翻译：混合多级存储器架构
公开(公告)号：US20150006805A1
公开(公告)日：2015-01-01
申请号：US13931701
申请日：2013-06-28
申请人： DANNIE G. FEEKES , SHLOMO RAIKIN , BLAISE FANNING , JOYDEEP RAY , JULIUS MANDELBLAT , ARIEL BERKOVITS , ERAN SHIFER , ZVIKA GREENFIELD , EVGENY BOLOTIN
发明人： DANNIE G. FEEKES , SHLOMO RAIKIN , BLAISE FANNING , JOYDEEP RAY , JULIUS MANDELBLAT , ARIEL BERKOVITS , ERAN SHIFER , ZVIKA GREENFIELD , EVGENY BOLOTIN
IPC分类号： G06F3/06
CPC分类号： G06F12/0893 , G06F1/32 , G06F1/3275 , G06F12/063 , G06F12/08 , G06F12/0866 , G06F2212/205 , G06F2212/206 , G06F2212/281 , G06F2212/604 , G06F2212/608 , Y02D10/13 , Y02D10/14
摘要： Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.
摘要翻译：描述了混合多层存储器架构技术。片上系统（SOC）包括多个功能单元和耦合到功能单元的多级存储器控制器（MLMC）。 MLMC耦合到混合多级存储器架构，其包括位于SOC的封装上的第一级动态随机存取存储器（近似存储器）和位于该存储器的二级DRAM（远存储器））的混合多级存储器架构 SOC的脱离包装。 MLMC将第一级DRAM和第二级DRAM作为连续可寻址存储空间，并将第一级DRAM提供给软件，作为第二级DRAM存储容量的附加存储容量。第一级DRAM不存储二级DRAM的内容副本。

43. 发明申请

US20140192069A1 APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER INSTRUCTION 有权
标题翻译：用于记忆级别生产者消费者指令的装置和方法
公开(公告)号：US20140192069A1
公开(公告)日：2014-07-10
申请号：US13994122
申请日：2011-12-21
申请人： Shlomo Raikin , Raanan Sade , Robert Valentine , Julius Yuli Mandelblat , Ron Shalev , Larisa Novakovsky
发明人： Shlomo Raikin , Raanan Sade , Robert Valentine , Julius Yuli Mandelblat , Ron Shalev , Larisa Novakovsky
IPC分类号： G06F13/38 , G06F13/16 , G06T1/60 , G06F12/08 , G06T1/20
CPC分类号： G06F12/0811 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3881 , G06F12/0866 , G06F13/1673 , G06F13/38 , G06T1/20 , G06T1/60 , G09G5/006
摘要： An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.
摘要翻译：描述了一种有效地将数据从中央处理单元（CPU）的核心传输到图形处理单元（GPU）的装置和方法。例如，一种方法的一个实施例包括：将数据写入CPU的核心内的缓冲器，直到指定的数据量被写入为止; 在检测到指定量的数据已被写入时，响应地产生驱逐周期，驱逐循环使数据从缓冲器传送到可由核心和GPU访问的高速缓存; 设置指示以向GPU指示数据在高速缓存中可用; 并且在GPU检测到指示时，在从GPU接收到读取信号时，从高速缓存提供数据给GPU。

44. 发明申请

US20140189254A1 Snoop Filter Having Centralized Translation Circuitry and Shadow Tag Array 有权
标题翻译：具有集中翻译电路和阴影标签阵列的窥探滤波器
公开(公告)号：US20140189254A1
公开(公告)日：2014-07-03
申请号：US13730956
申请日：2012-12-29
申请人： Ilan PARDO , NIRANJAN COORAY , Stanislav SHWARTSMAN , Shlomo RAIKIN
发明人： Ilan PARDO , NIRANJAN COORAY , Stanislav SHWARTSMAN , Shlomo RAIKIN
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0831 , G06F12/1027 , G06F12/1063
摘要： A processor is described that includes a plurality of processing cores. The processor includes an interconnection network coupled to each of said processing cores. The processor includes snoop filter logic circuitry coupled to the interconnection network and associated with coherence plane logic circuitry of the processor. The snoop filter logic circuitry contains circuitry to hold information that identifies not only which of the processing cores are caching specific cache lines that are cached by the processing cores, but also, where in respective caches of the processing cores the cache lines are cached.
摘要翻译：描述了包括多个处理核心的处理器。处理器包括耦合到每个所述处理核心的互连网络。处理器包括连接到互连网络并与处理器的相干平面逻辑电路相关联的窥探滤波器逻辑电路。监听滤波器逻辑电路包含用于保存信息的电路，该信息不仅识别哪个处理核心缓存由处理核心高速缓存的特定高速缓存线，而且在处理核心的高速缓存中缓存高速缓存行被缓存。

45. 发明申请

US20140006746A1 VIRTUAL MEMORY ADDRESS RANGE REGISTER 有权
标题翻译：虚拟内存地址范围注册
公开(公告)号：US20140006746A1
公开(公告)日：2014-01-02
申请号：US13538900
申请日：2012-06-29
申请人： Gur Hildesheim , Shlomo Raikin , Ittai Anati , Gideon Gerzon , Uday Savagaonkar , Francis Mckeen , Carlos Rozas , Michael Goldsmith , Prashant Dewan
发明人： Gur Hildesheim , Shlomo Raikin , Ittai Anati , Gideon Gerzon , Uday Savagaonkar , Francis Mckeen , Carlos Rozas , Michael Goldsmith , Prashant Dewan
IPC分类号： G06F12/10
CPC分类号： G06F12/109 , G06F12/0284 , G06F12/1036 , G06F2212/656 , G06F2212/657
摘要： Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
摘要翻译：公开了包括虚拟地址存储器范围寄存器的装置和方法的实施例。在一个实施例中，处理器包括存储器接口，地址转换硬件和虚拟存储器地址比较硬件。存储器接口是使用物理内存地址访问系统内存。地址转换硬件是支持将虚拟内存地址转换为物理内存地址。虚拟存储器地址由软件用于访问处理器的虚拟存储器地址空间中的虚拟存储器位置。虚拟内存地址比较硬件是确定虚拟内存地址是否在虚拟内存地址范围内。

46. 发明授权

US08370577B2 Metaphysically addressed cache metadata 有权
标题翻译：形而上学的缓存元数据
公开(公告)号：US08370577B2
公开(公告)日：2013-02-05
申请号：US12493165
申请日：2009-06-26
申请人： Gad Sheaffer , David Callahan , Jan Gray , Ali-Reza Adl-Tabatabai , Shlomo Raikin
发明人： Gad Sheaffer , David Callahan , Jan Gray , Ali-Reza Adl-Tabatabai , Shlomo Raikin
IPC分类号： G06F12/00
CPC分类号： G06F17/30997 , G06F12/0802 , G06F12/109
摘要： Storing metadata that is disjoint from corresponding data by storing the metadata to the same address as the corresponding data but in a different address space. A metadata store instruction includes a storage address for the metadata. The storage address is the same address as that for data corresponding to the metadata, but the storage address when used for the metadata is implemented in a metadata address space while the storage address, when used for the corresponding data is implemented in a different data address space. As a result of executing the metadata store instruction, the metadata is stored at the storage address. A metadata load instruction includes the storage address for the metadata. As a result of executing the metadata load instruction, the metadata stored at the address is received. Some embodiments may further implement a metadata clear instruction which clears any entries in the metadata address space.
摘要翻译：通过将元数据存储到与相应数据相同的地址但在不同的地址空间中，存储与相应数据不相关的元数据。元数据存储指令包括元数据的存储地址。存储地址与对应于元数据的数据的地址相同，但是当用于元数据的存储地址被实现在元数据地址空间中，而当用于相应数据的存储地址被实现在不同的数据地址空间。作为执行元数据存储指令的结果，元数据被存储在存储地址处。元数据加载指令包括元数据的存储地址。作为执行元数据加载指令的结果，接收存储在地址处的元数据。一些实施例可以进一步实现清除元数据地址空间中的任何条目的元数据清除指令。

47. 发明授权

US08341356B2 Protected cache architecture and secure programming paradigm to protect applications 有权
标题翻译：保护缓存架构和安全编程范例来保护应用程序
公开(公告)号：US08341356B2
公开(公告)日：2012-12-25
申请号：US13099479
申请日：2011-05-03
申请人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
发明人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
IPC分类号： G06F12/06
CPC分类号： G06F12/0802 , G06F12/0804 , G06F12/1491 , G06F21/10
摘要： Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventing the other protection mechanisms. A protected cache may be used as a building block to enhance the security of applications trying to create, manage and protect secure data. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供了一种安全编程范例和受保护的高速缓存，其使得处理器能够处理秘密/专用信息，同时防止恶意应用程序通过规避其他保护机制来访问该信息。受保护的缓存可以用作构建块，以增强试图创建，管理和保护安全数据的应用程序的安全性。描述和要求保护其他实施例。

48. 发明授权

US07975129B2 Selective hardware lock disabling 有权
标题翻译：选择性硬件锁定禁用
公开(公告)号：US07975129B2
公开(公告)日：2011-07-05
申请号：US12562457
申请日：2009-09-18
申请人： Shlomo Raikin , Gad Sheaffer , Doron Orenstlen
发明人： Shlomo Raikin , Gad Sheaffer , Doron Orenstlen
IPC分类号： G06F9/312
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/526
摘要： Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire the LAO, a unit to cause the ROB to selectively disable the lock, and a unit to snoop a buffer. The apparatus may, based on the snooping, selectively abort a transaction associated with the CS.
摘要翻译：描述了控制重排序缓冲器（ROB）以选择性地执行功能性硬件锁定禁止（HLD）。一个设备实施例包括一个单元，以使得ROB能够在识别与关键部分（CS）入口点相关联的锁定获取操作（LAO）时选择性地禁用锁定，该选择单元选择性地退出LAO，该单元使得ROB 选择性地禁用该锁，以及一个单元来窥探缓冲区。该设备可以基于窥探，选择性地中止与CS相关联的事务。

49. 发明申请

US20100169894A1 REGISTERING A USER-HANDLER IN HARDWARE FOR TRANSACTIONAL MEMORY EVENT HANDLING 有权
标题翻译：在硬件中注册用户处理事务处理事务处理
公开(公告)号：US20100169894A1
公开(公告)日：2010-07-01
申请号：US12346518
申请日：2008-12-30
申请人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin
发明人： Gad Sheaffer , Shlomo Raikin , Vadim Bassin
IPC分类号： G06F9/46
CPC分类号： G06F9/466 , G06F9/528
摘要： A method and apparatus for registering a user-handler in hardware for transactional memory is herein described. A user-accessible register is to hold a reference to a transactional handler. An event register may also be provided to specify handler events, which may be done utilizing user-level software, privileged software, or by hardware. When an event is detected execution vectors to the transaction handler based on the reference to the transactional handler held in the user-accessible register. The transactional handler handles the event and then execution returns to normal flow.
摘要翻译：这里描述用于在用于事务存储器的硬件中注册用户处理程序的方法和装置。用户可访问的寄存器用于保存对事务处理程序的引用。还可以提供事件寄存器来指定处理程序事件，这可以使用用户级软件，特权软件或硬件来完成。当根据对用户可访问寄存器中保存的事务处理程序的引用检测事件到事务处理程序的执行向量时。事务处理程序处理事件，然后执行返回正常流程。

50. 发明申请

US20090070774A1 LIVE LOCK FREE PRIORITY SCHEME FOR MEMORY TRANSACTIONS IN TRANSACTIONAL MEMORY 有权
标题翻译：实时锁定用于存储器交易的优先存储器
公开(公告)号：US20090070774A1
公开(公告)日：2009-03-12
申请号：US11854175
申请日：2007-09-12
申请人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
发明人： Shlomo Raikin , Shay Gueron , Gad Sheaffer
IPC分类号： G06F9/46
CPC分类号： G06F9/524 , G06F9/466
摘要： A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value. When the FMV counter is at a predetermined number of aborts the counting logic is reset to avoid live lock.
摘要翻译：这里描述了用于在事务执行期间避免实时锁定的方法和装置。计数逻辑用于跟踪每个处理元素的成功提交事务。当在多个处理元件之间的事务之间检测到数据冲突时，以较低的计数逻辑值提供给处理元件的优先级。此外，如果值相同，则具有较低识别值的处理元件被赋予优先级，即允许在其他事务被中止时继续。为了避免在具有预定的计数逻辑值（例如最大计数值）的处理元件之间的实时锁定，当一个处理元件达到预定计数值时，所有计数器都被重置。此外，当计数逻辑处于最大值时，可以提供在最大值（FMV）计数器上的故障来计数事务的中止次数。当FMV计数器处于预定数量的中止时，计数逻辑被复位以避免实时锁定。

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