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41. 发明授权

US5764573A Semiconductor device capable of externally and readily identifying set bonding optional function and method of identifying internal function of semiconductor device 失效
标题翻译：能够外部容易地识别设定接合的半导体器件的可选功能和识别半导体器件的内部功能的方法
公开(公告)号：US5764573A
公开(公告)日：1998-06-09
申请号：US787803
申请日：1997-01-23
申请人： Masayuki Iketani , Shigeki Ohbayashi
发明人： Masayuki Iketani , Shigeki Ohbayashi
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/00 , G11C11/401 , G11C29/02 , H03K5/12 , G11C13/00
CPC分类号： G11C29/02 , G06F11/006
摘要： A checking circuit is provided which electrically and selectively connects a pad to which an internal circuit is connected, to a reference potential source node, in accordance with a potential of a special pad, when activated. The checking circuit is activated when a burn-in mode detection signal is activated. By detecting a leak current of a pin terminal to which the pad connected to the circuit is electrically connected, the potential of the special pad, that is, set internal function, can be externally identified. Accordingly, a bonding option function of which internal function is set in accordance with the potential of the bonding pad, can be externally detected in a non-destructive manner.
摘要翻译：提供了一种检查电路，其在被激活时根据特殊焊盘的电位将选择性地连接内部电路的焊盘电连接到参考电位源节点。当激活老化模式检测信号时，检查电路被激活。通过检测连接到电路的焊盘电连接的引脚端子的泄漏电流，可以从外部识别专用焊盘的电位，即设置内部功能。因此，可以以非破坏性的方式外部检测根据接合焊盘的电位设定内部功能的接合选择功能。

42. 发明授权

US5506805A Static semiconductor memory device having circuitry for enlarging write recovery margin 失效
标题翻译：具有放大写恢复余量的电路的静态半导体存储器件
公开(公告)号：US5506805A
公开(公告)日：1996-04-09
申请号：US402212
申请日：1995-03-10
申请人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
发明人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
IPC分类号： G11C11/41 , G11C7/14 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/417 , G11C11/419 , G11C29/00 , G11C7/00
CPC分类号： G11C29/78 , G11C11/417 , G11C11/419 , G11C7/14 , G11C7/22
摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.
摘要翻译：延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。写入门响应于列选择信号将位线连接到本地写数据总线。延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改善操作特性和可靠性的各种布置。

43. 发明授权

US5274597A Semiconductor memory device capable of driving divided word lines at high speed 失效
标题翻译：能够高速驱动分割字线的半导体存储器件
公开(公告)号：US5274597A
公开(公告)日：1993-12-28
申请号：US767315
申请日：1991-09-30
申请人： Shigeki Ohbayashi , Atsushi Ohba , Toru Shiomi
发明人： Shigeki Ohbayashi , Atsushi Ohba , Toru Shiomi
IPC分类号： G11C11/41 , G11C11/418 , H01L21/8244 , H01L27/11 , G11C7/00
CPC分类号： G11C11/418
摘要： A divided word line driving circuit applicable to a static random access memory (SRAM) employing a divided word line method is disclosed. When a divided word line is activated, the potential at the input of an inverter for driving the word line is brought to a low level. When the input signals S1 and S2 are both at a low level, the divided word line is brought to an inactive state. The input of the inverter is charged by a transistor 101 in addition to a transistor 102 which is always on. In other words, transistor 101 contributes to accelerating charging of the input of the inverter. Consequently, the potential of the divided word line is made to rise at high speed, so that access operation at high speed can be achieved. The circuit is implemented with a small number of transistors, so that it becomes also possible to enhance the degree of integration of a SRAM.
摘要翻译：公开了一种适用于采用分割字线方法的静态随机存取存储器（SRAM）的分割字线驱动电路。当分割字线被激活时，用于驱动字线的逆变器的输入端的电位变为低电平。当输入信号S1和S2都处于低电平时，分割字线处于非活动状态。除了始终导通的晶体管102之外，反相器的输入由晶体管101充电。换句话说，晶体管101有助于加速逆变器的输入的充电。因此，使分割字线的电位高速上升，从而可以实现高速的存取操作。该电路由少量的晶体管实现，使得还可以提高SRAM的集成度。

44. 发明授权

US5138201A Sense amplifier operable under variable power supply voltage 失效
标题翻译：感应放大器在可变电源电压下可操作
公开(公告)号：US5138201A
公开(公告)日：1992-08-11
申请号：US542225
申请日：1990-06-22
申请人： Shigeki Ohbayashi , Atsushi Ohba
发明人： Shigeki Ohbayashi , Atsushi Ohba
IPC分类号： G11C11/419 , G11C7/06 , G11C11/416
CPC分类号： G11C7/062
摘要： Disclosed is a sense amplifier employing an emitter coupled logic (ECL) circuit. A constant voltage generating circuit independent of a change or a fluctuation of a power supply voltage level is provided. Two current-mirror circuits supply constant currents to the ECL circuit based on a generated constant voltage. Since a constant current independent of the change of power supply voltage level is supplied to the ECL circuit, the ECL circuit reliably converts a small potential difference generated between I/O lines into a current signal. Accordingly, no erroneous reading operation is performed.
摘要翻译：公开了采用发射极耦合逻辑（ECL）电路的读出放大器。提供了与电源电压电平的变化或波动无关的恒压发生电路。两个电流镜电路基于产生的恒定电压向ECL电路提供恒定电流。由于独立于电源电压电平变化的恒定电流被提供给ECL电路，因此ECL电路将I / O线之间产生的小电位差可靠地转换为电流信号。因此，不执行错误的读取操作。

45. 发明授权

US08743645B2 Semiconductor memory device for stably reading and writing data 有权
标题翻译：用于稳定读取和写入数据的半导体存储器件
公开(公告)号：US08743645B2
公开(公告)日：2014-06-03
申请号：US13325945
申请日：2011-12-14
申请人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
发明人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/06 , G11C5/14 , G11C8/08 , G11C11/417 , G11C11/418
摘要： In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.
摘要翻译：在半导体存储器件中，静态存储单元以行和列排列，字线对应于相应的存储单元行，并且字线驱动器对应于字线。单元电源线对应于相应的存储单元列并且耦合到相应列中的存储器单元的单元电源节点。向下电源线被布置成对应于相应的存储单元列，保持在数据读取中的接地电压并且在数据写入中被电浮动。写入辅助元件对应于单电池电源线布置，并且根据写入列指示信号，用于停止向所选列中的单元电源线提供单元电源电压，并且用于耦合布置的单元电源线对应于所选列至少至相应列上的下电源线。

46. 发明授权

US08395932B2 Semiconductor storage device and method of fabricating the same 有权
公开(公告)号：US08395932B2
公开(公告)日：2013-03-12
申请号：US12827668
申请日：2010-06-30
申请人： Hidemoto Tomita , Shigeki Ohbayashi , Yoshiyuki Ishigaki
发明人： Hidemoto Tomita , Shigeki Ohbayashi , Yoshiyuki Ishigaki
IPC分类号： G11C11/41 , G11C5/02 , G11C5/06
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L2924/0002 , Y10S257/903 , Y10S257/904 , H01L2924/00
摘要： A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.

47. 发明申请

US20120087198A1 SEMICONDUCTOR MEMORY DEVICE WITH ADJUSTABLE SELECTED WORK LINE POTENTIAL UNDER LOW VOLTAGE CONDITION 有权
标题翻译：在低电压条件下具有可调节选择的工作线电位的半导体存储器件
公开(公告)号：US20120087198A1
公开(公告)日：2012-04-12
申请号：US13325945
申请日：2011-12-14
申请人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
发明人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/06 , G11C5/14 , G11C8/08 , G11C11/417 , G11C11/418
摘要： A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.
摘要翻译：针对每个字线布置根据存储单元晶体管的阈值电压的波动来调整在选择字线时的电压电平的电平移动元件。该电平移动元件降低驱动器电源电压，并将电平移位电压发送到所选择的字线上。电平移位元件可以用用于根据存储单元晶体管的阈值电压电平来拉低字线电压的下拉元件来代替。在任一情况下，可以根据存储单元晶体管的阈值电压的波动来调整所选字线电压电平，而不使用另一电源系统。因此，电源电路不复杂，即使在低电源电压下也可以实现能够稳定地读写数据的半导体存储器件。

48. 发明申请

US20070177416A1 Semiconductor storage device and method of fabricating the same 审中-公开
标题翻译：半导体存储装置及其制造方法
公开(公告)号：US20070177416A1
公开(公告)日：2007-08-02
申请号：US11727040
申请日：2007-03-23
申请人： Hidemoto Tomita , Shigeki Ohbayashi , Yoshiyuki Ishigaki
发明人： Hidemoto Tomita , Shigeki Ohbayashi , Yoshiyuki Ishigaki
IPC分类号： G11C17/00
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L2924/0002 , Y10S257/903 , Y10S257/904 , H01L2924/00
摘要： A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.
摘要翻译：半导体存储装置包括存储单元阵列，多个字线，多个位线，第一栅极布线元件3a，3b，第二栅极布线元件3c，3d，第一连接器5a， 5b和第二连接器5c，5d。每个存储单元10具有第一和第二组，其具有驱动晶体管11，负载晶体管12和存取晶体管13.字线沿着第一方向彼此平行布置。位线沿垂直于第一方向的第二方向彼此平行布置。第一栅极布线元件包括第一驱动晶体管的栅电极和第一负载晶体管，并且具有在相对侧具有直线的矩形形状。第二栅极布线元件包括存取晶体管的栅电极，并且具有在相对侧具有直线的矩形形状。

49. 发明申请

US20070030741A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070030741A1
公开(公告)日：2007-02-08
申请号：US11492031
申请日：2006-07-25
申请人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
发明人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/06 , G11C5/14 , G11C8/08 , G11C11/417 , G11C11/418
摘要： A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.
摘要翻译：针对每个字线布置根据存储单元晶体管的阈值电压的波动来调整在选择字线时的电压电平的电平移动元件。该电平移动元件降低驱动器电源电压，并将电平移位电压发送到所选择的字线上。电平移位元件可以用用于根据存储单元晶体管的阈值电压电平来拉低字线电压的下拉元件来代替。在任一情况下，可以根据存储单元晶体管的阈值电压的波动来调整所选字线电压电平，而不使用另一电源系统。因此，电源电路不复杂，即使在低电源电压下也可以实现能够稳定地读写数据的半导体存储器件。

50. 发明授权

US06812574B2 Semiconductor storage device and method of fabricating the same 有权
标题翻译：半导体存储装置及其制造方法
公开(公告)号：US06812574B2
公开(公告)日：2004-11-02
申请号：US10190715
申请日：2002-07-09
申请人： Hidemoto Tomita , Shigeki Ohbayashi , Yoshiyuki Ishigaki
发明人： Hidemoto Tomita , Shigeki Ohbayashi , Yoshiyuki Ishigaki
IPC分类号： H01L2348
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L2924/0002 , Y10S257/903 , Y10S257/904 , H01L2924/00
摘要： A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.
摘要翻译：半导体存储装置包括存储单元阵列，多个字线，多个位线，第一栅极布线元件3a，3b，第二栅极布线元件3c，3d，第一连接器5a，5b和第二栅极布线元件连接器5c，5d。每个存储单元10具有第一和第二组，其具有驱动晶体管11，负载晶体管12和存取晶体管13.字线沿着第一方向彼此平行布置。位线沿垂直于第一方向的第二方向彼此平行布置。第一栅极布线元件包括第一驱动晶体管的栅电极和第一负载晶体管，并且具有在相对侧具有直线的矩形形状。第二栅极布线元件包括存取晶体管的栅电极，并且具有在相对侧具有直线的矩形形状。

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