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41. 发明授权

US08500044B2 Multiple nozzle differential fluid delivery head 有权
标题翻译：多个喷嘴差分流体输送头
公开(公告)号：US08500044B2
公开(公告)日：2013-08-06
申请号：US11749558
申请日：2007-05-16
申请人： Michael M. Sawalski , Michael J. Skalitzky , Nitin Sharma , Padma Prabodh Varanasi , Yong Chen , Allen D. Miller
发明人： Michael M. Sawalski , Michael J. Skalitzky , Nitin Sharma , Padma Prabodh Varanasi , Yong Chen , Allen D. Miller
IPC分类号： E03D9/02 , B05B1/14 , B05B1/12 , B05B1/02
CPC分类号： B67D7/00 , B05B1/14 , B05B1/3421 , B05B3/0486 , E03D9/005 , E03D9/032
摘要： A multiple nozzle differential fluid delivery head is disclosed. The fluid delivery head includes a body that defines a fluid chamber having a longitudinal axis. The body includes an inlet for connection to a fluid source, and the inlet is in fluid communication with the fluid chamber. The fluid delivery head includes a plurality of outlet ports connected to and extending away from the body. Each outlet port has an interior space in fluid communication with the fluid chamber. The fluid delivery head includes a nozzle insert removably secured in an outer end of each outlet port. At least one nozzle insert has a fluid delivery aperture in fluid communication with the interior space of its associated outlet port for delivering fluid out of the interior space of its associated outlet port. One or more of the outlet ports is angled away from a plane normal to the axis of the fluid delivery head.
摘要翻译：公开了一种多喷嘴差动流体输送头。流体输送头包括限定具有纵向轴线的流体室的主体。主体包括用于连接到流体源的入口，并且入口与流体室流体连通。流体输送头包括连接到主体并远离主体的多个出口。每个出口端口具有与流体室流体连通的内部空间。流体输送头包括可移除地固定在每个出口的外端的喷嘴插件。至少一个喷嘴插件具有与其相关联的出口端口的内部空间流体连通的流体输送孔，用于将流体输送出其相关联的出口端口的内部空间。一个或多个出口端口与垂直于流体输送头的轴线的平面倾斜。

42. 发明申请

US20130008982A1 INSERT FOR DISPENSING A COMPRESSED GAS PRODUCT, SYSTEM WITH SUCH AN INSERT, AND METHOD OF DISPENSING A COMPRESSED GAS PRODUCT 有权
标题翻译：用于分配压缩气体产品的插入件，具有这种插件的系统以及分配压缩气体产品的方法
公开(公告)号：US20130008982A1
公开(公告)日：2013-01-10
申请号：US13428945
申请日：2012-03-23
申请人： Bhaveshkumar Shah , Nitin Sharma
发明人： Bhaveshkumar Shah , Nitin Sharma
IPC分类号： B05B1/34
CPC分类号： A61L9/14 , A01M1/2038 , A61L2209/134 , B05B1/3421 , B05B1/3426 , B05B1/3436 , B05B1/3478 , B05B7/10 , B65D83/206 , B65D83/48 , Y10T137/0318 , Y10T137/2087
摘要： An insert, a system, and a method are provided for dispensing a compressed gas product. The insert includes a swirl chamber, inlet ports to the swirl chamber, and an outlet orifice. The insert has specifically configured parameters relating to the diameter of the swirl chamber, the diameter of the outlet orifice, the length of the outlet orifice, and the depth of the swirl chamber. The insert, system, and method can provide a dispensed compressed gas product with a remarkably constant flow rate and with a remarkably constant particle size.
摘要翻译：提供插入件，系统和方法来分配压缩气体产品。插入件包括旋流室，到涡流室的入口和出口孔。该插入件具有与涡流室的直径，出口孔的直径，出口孔的长度以及涡流室的深度有关的参数。插入物，系统和方法可以提供具有非常恒定的流速并具有非常恒定的粒度的分配的压缩气体产物。

43. 发明申请

US20120273978A1 Centrifugal Fan Device 有权
标题翻译：离心式风扇装置
公开(公告)号：US20120273978A1
公开(公告)日：2012-11-01
申请号：US13096527
申请日：2011-04-28
申请人： Nitin Sharma
发明人： Nitin Sharma
IPC分类号： B01F3/04 , B05B3/04
CPC分类号： A61L9/122 , A01M1/2033 , A01M1/2044 , A61L9/127
摘要： An apparatus for delivering a compound includes a reservoir containing a compound to be delivered to the environment of use. The compound includes fragrances and insecticides. A compound permeable substrate includes a wick which extends from the substrate into the reservoir. A centrifugal fan is operatively associated with the compound permeable substrate to force air over the substrate when the fan is operational. A cover is disposed over the centrifugal fan in which the cover has at least one aperture on a top surface and provides for a side air passage from the centrifugal fan to the environment.
摘要翻译：用于输送化合物的装置包括储存器，该贮存器包含要输送到使用环境的化合物。该化合物包括香料和杀虫剂。复合可渗透基底包括从基底延伸到储存器中的芯。离心风扇可操作地与复合可渗透衬底相关联，以在风扇可操作时迫使空气流过衬底。盖子设置在离心风扇上方，其中盖子在顶表面上具有至少一个孔口，并提供从离心风扇到环境的侧面空气通道。

44. 外观设计

USD666705S1 Wick 有权
公开(公告)号：USD666705S1
公开(公告)日：2012-09-04
申请号：US29369532
申请日：2010-09-09
申请人： Daniel A. Andersen , Kylie L. Levake , Kenneth W. Michaels , David J. Schram , Nitin Sharma , James T. Walker , Steven V. Bisbikis , Jason R. Gebhardt
设计人： Daniel A. Andersen , Kylie L. Levake , Kenneth W. Michaels , David J. Schram , Nitin Sharma , James T. Walker , Steven V. Bisbikis , Jason R. Gebhardt

45. 发明申请

US20120024975A1 SYSTEM FOR AND METHOD OF CONSISTENTLY EMITTING A VOLATILE MATERIAL 有权
标题翻译：一致挥发挥发性物质的系统和方法
公开(公告)号：US20120024975A1
公开(公告)日：2012-02-02
申请号：US13196089
申请日：2011-08-02
申请人： Nitin Sharma , Maciej K. Tasz , Ross Peter Jones
发明人： Nitin Sharma , Maciej K. Tasz , Ross Peter Jones
IPC分类号： A61L9/04
CPC分类号： A61L9/037 , A01M1/2044 , A61L9/127
摘要： A system for consistently emitting a volatile material includes a volatile material dispenser having a diffusion element. The system further includes a refill adapted for disposal within the volatile material dispenser and including a container having a volatile material disposed therein and a wick having a first end disposed in contact with the volatile material in the container and a second end extending out of the container. A time constant for (Parameter 4) for the system is less than or equal to about 1.0 hour when estimated using the equation: Predicted mass change=Parameter4+(Parameter3*T)+(Parameter2*exp(−T/Parameter1)).
摘要翻译：用于一致地发射挥发性材料的系统包括具有扩散元件的挥发性材料分配器。所述系统还包括适于在所述挥发性物料分配器内处理并包括其中设置有挥发性物质的容器的填充物和具有设置成与所述容器中的挥发性物质接触的第一端的芯和从容器延伸出的第二端。当使用以下等式估计时，系统的（参数4）的时间常数小于或等于约1.0小时：预测质量变化= Parameter4 +（Parameter3 * T）+（Parameter2 * exp（-T / Parameter1））。

46. 发明申请

US20090183135A1 Method and Device for Identifying and Implementing Flexible Logic Block Logic for Easy Engineering Changes 有权
标题翻译：用于识别和实现灵活逻辑块逻辑的方法和设备，用于简单的工程变更
公开(公告)号：US20090183135A1
公开(公告)日：2009-07-16
申请号：US12014240
申请日：2008-01-15
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).
摘要翻译：芯片设计方法。该方法包括识别工程可变逻辑，并用灵活的逻辑块（FLB）替换所识别的工程可变逻辑。

47. 发明申请

US20090153324A1 DESIGN STRUCTURE FOR MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT 失效
标题翻译：在集成电路中测量功耗的设计结构
公开(公告)号：US20090153324A1
公开(公告)日：2009-06-18
申请号：US12046501
申请日：2008-03-12
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
IPC分类号： G08B21/00
CPC分类号： G01R31/31721
摘要： An design structure for measuring power consumed during operation of an integrated circuit. The design structure including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.
摘要翻译：一种用于测量集成电路运行期间消耗的功率的设计结构。该设计结构包括：具有输入和输出的数据处理电路，所述数据处理电路被配置为基于输入数据信号产生输出数据信号; 功率测量电路，被配置为测量由所述输入信号产生所述输出信号时由所述处理电路消耗的电力量;连接在所述处理电路和所述处理电路的电源之间的所述功率测量电路; 以及存储元件，被配置为存储包含表示由处理电路消耗的电力量的值的标签，用于从输入数据信号生成输出数据信号，以及（a）输入数据信号的输入数据或（b ）指向输入数据信号的输入数据的指针。

48. 发明申请

US20090045836A1 ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE 审中-公开
标题翻译：柔性逻辑块的ASIC逻辑库和使用工程变更的方法
公开(公告)号：US20090045836A1
公开(公告)日：2009-02-19
申请号：US11838929
申请日：2007-08-15
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： H03K19/173 , G06F17/50
CPC分类号： G06F17/505
摘要： A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in the design process.
摘要翻译：芯片设计方法和集成电路芯片。该方法包括在网络列表中提供多个逻辑门，其中每个逻辑门包括至少一个备用输入，合成网络列表，以及在设计过程的后期连接用于执行工程变更的备用输入。

49. 发明授权

US07362840B2 Circuit and method for adjusting timing alignment using programmable codes 有权
标题翻译：使用可编程代码调整定时对准的电路和方法
公开(公告)号：US07362840B2
公开(公告)日：2008-04-22
申请号：US10990367
申请日：2004-11-18
申请人： Terence L. Johnson , Timothy R. Miller , Nitin Sharma
发明人： Terence L. Johnson , Timothy R. Miller , Nitin Sharma
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H04B1/7183 , H04B1/71632
摘要： A method is provided for adjusting timing alignment in which a receiver generates a plurality of imbalanced correction codes (1310), and square waves both having the same frequency. The receiver mixes the imbalanced correction codes with the square waves to create a mixed signal (1320), and integrates the mixed signal over a correction code period to generate a signal power value (1330). The receiver adjusts a phase of the square wave in a first direction when the signal power value satisfies a first criterion (1340, 1350), and in a second direction when the signal power value satisfies a second criterion (1340, 1360). Each imbalanced correction code is symmetrical. And a total integrated value of one of the imbalanced correction codes over the correction code period is either above a first threshold, or below a second threshold, the first threshold being greater than or equal to the second threshold.
摘要翻译：提供了一种用于调整接收器产生多个不平衡校正码（1310）的定时对准的方法以及具有相同频率的方波。接收器将不平衡校正码与方波混合以产生混合信号（1320），并且通过校正码周期对混合信号进行积分以产生信号功率值（1330）。当信号功率值满足第一标准（1340,1350）时，接收器在第一方向上调整方波的相位，并且当信号功率值满足第二标准（1340,1360）时，第二方向调整方波的相位。每个不平衡校正码是对称的。并且在校正码周期中不平衡校正码之一的总积分值大于第一阈值或低于第二阈值，第一阈值大于或等于第二阈值。

50. 发明申请

US20070063883A1 Pipelined analog to digital converter 审中-公开
标题翻译：流水线模数转换器
公开(公告)号：US20070063883A1
公开(公告)日：2007-03-22
申请号：US11229599
申请日：2005-09-20
申请人： Phuong Huynh , Nitin Sharma
发明人： Phuong Huynh , Nitin Sharma
IPC分类号： H03M1/12
CPC分类号： H03M1/1205 , H03M1/361
摘要： A circuit is provided for receiving an analog signal and providing a digital signal. It includes pre-amplifiers (601, 603, 605, 607), where each pre-amplifier (601, 603, 605, 607) receives an analog signal (Vin) and a respective reference signal (REF1-REFn). Each of the pre-amplifiers (601, 603, 605, 607) produces an output signal responsive to the analog signal and the respective reference signal. For each of the pre-amplifiers (601, 603, 605, 607), there is provided two or more latches (615, 617, 619, 621, 623, 625) corresponding thereto. Each of the latches (615, 617, 619, 621, 623, 625) receives the output signal and a clock signal and produces a respective digital signal responsive thereto, the clock signal being interleaved. For each of the pre-amplifiers (601, 603, 605, 607), there is a multiplexer (627, 629, 631) corresponding thereto. The multiplexer (627, 629, 631) multiplexes between the respective digital signals to produce a bit in a digital signal.
摘要翻译：提供用于接收模拟信号并提供数字信号的电路。它包括预放大器（601,603,605,607），其中每个前置放大器（601,603,605,607）接收模拟信号（Vin）和相应的参考信号（REF 1 -REFn）。每个前置放大器（601,603,605,607）产生响应于模拟信号和相应参考信号的输出信号。对于每个前置放大器（601,603,605,607），提供两个或多个对应于其的锁存器（615,617,619,621,663,625）。每个锁存器（615,617,619,621,623,625）接收输出信号和时钟信号，并响应于此产生相应的数字信号，时钟信号被交织。对于每个前置放大器（601,603,605,607），存在对应于其的多路复用器（627,629,631）。复用器（627,629,631）在相应的数字信号之间复用以产生数字信号中的位。

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