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41. 发明申请

US20080122107A1 POLY SILICON HARD MASK 审中-公开
公开(公告)号：US20080122107A1
公开(公告)日：2008-05-29
申请号：US11534553
申请日：2006-09-22
申请人： Jang-Shiang Tsai , Jyu-Horng Shieh , Ju-Wang Hsu , De-Fang Chen , Chia-Hui Lin , Syun-Ming Jang
发明人： Jang-Shiang Tsai , Jyu-Horng Shieh , Ju-Wang Hsu , De-Fang Chen , Chia-Hui Lin , Syun-Ming Jang
IPC分类号： H01L23/52 , H01L21/311
CPC分类号： H01L21/31144 , H01L21/76802 , H01L21/76811
摘要： A method of forming an opening on a low-k dielectric layer using a polysilicon hard mask rather than a metal hard mask as used in prior art. A polysilicon hard mask is formed over a low-k dielectric layer and a photoresist layer is formed over the polysilicon hard mask. The photoresist layer is patterned and the polysilicon hard mask is etched with a gas plasma to create exposed portions of the low-k dielectric layer. The photoresist layer in stripped prior to the etching of the exposed portions of the low-k dielectric layer to avoid damage to the low-k dielectric layer.
摘要翻译：使用现有技术中使用的多晶硅硬掩模而不是金属硬掩模在低k电介质层上形成开口的方法。在低k电介质层上形成多晶硅硬掩模，并且在多晶硅硬掩模上形成光致抗蚀剂层。对光致抗蚀剂层进行构图，并用气体等离子体蚀刻多晶硅硬掩模以产生低k电介质层的暴露部分。在蚀刻低k电介质层的暴露部分之前剥离的光致抗蚀剂层，以避免损坏低k电介质层。

42. 发明申请

US20080026518A1 Spacer layer etch method providing enhanced microelectronic device performance 有权
标题翻译：间隔层蚀刻方法提供增强的微电子器件性能
公开(公告)号：US20080026518A1
公开(公告)日：2008-01-31
申请号：US11495348
申请日：2006-07-28
申请人： Hung Der Su , Ju-Wang Hsu , Yi-Chun Huang , Shien-Yang Wu , Yung-Shun Chen , Tung-Heng Shie , Yuan-Hung Chiu , Jyh-Huei Chen , Jhon Jhy Liaw
发明人： Hung Der Su , Ju-Wang Hsu , Yi-Chun Huang , Shien-Yang Wu , Yung-Shun Chen , Tung-Heng Shie , Yuan-Hung Chiu , Jyh-Huei Chen , Jhon Jhy Liaw
IPC分类号： H01L21/8234
CPC分类号： H01L29/6656 , H01L29/665 , H01L29/6653
摘要： A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.
摘要翻译：用于形成场效应晶体管器件的方法使用形成在栅电极上的共形间隔层。栅电极用作在半导体衬底内形成轻掺杂延伸区的掩模，并且栅电极和共形间隔层用作在半导体衬底内形成源极/漏极区的掩模。在保形间隔层上形成各向异性蚀刻形状的间隔物层，并进行各向同性蚀刻，以在形成硅化物层之前增强源/漏区的曝光。

43. 发明授权

US07259050B2 Semiconductor device and method of making the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07259050B2
公开(公告)日：2007-08-21
申请号：US10834474
申请日：2004-04-29
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze Liang Lee , Shih-Chang Chen , Ju-Wang Hsu
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze Liang Lee , Shih-Chang Chen , Ju-Wang Hsu
IPC分类号： H01L21/338
CPC分类号： H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å per minute using the same etchant.
摘要翻译：半导体器件包括衬底，设置在衬底上的栅极和形成在栅极两侧的衬底中的源极和漏极。该器件还包括具有形成在栅极的侧壁上的第一层和第二层的薄间隔物，其中使用相同的蚀刻剂，第一层和第二层具有至少每分钟至少10埃的湿蚀刻速率。

44. 发明授权

US07179701B2 Transistor with high dielectric constant gate and method for forming the same 有权
标题翻译：具有高介电常数栅极的晶体管及其形成方法
公开(公告)号：US07179701B2
公开(公告)日：2007-02-20
申请号：US10946494
申请日：2004-09-21
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Ju-Chien Chiang
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Ju-Chien Chiang
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/66553 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4975 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： A semiconductor device provides a gate structure that includes a conductive portion and a high-k dielectric material formed beneath and along sides of the conductive material. An additional gate dielectric material such as a gate oxide may be used in addition to the high-k dielectric material. The method for forming the structure includes forming an opening in an organic material, forming the high-k dielectric material and a conductive material within the opening and over the organic material then using chemical mechanical polishing to remove the high-k dielectric material and conductive material from regions outside the gate region.
摘要翻译：半导体器件提供了一种栅极结构，其包括在导电材料的下面和沿着导电材料的侧面形成的导电部分和高k电介质材料。除了高k电介质材料之外，可以使用诸如栅极氧化物的附加栅极介电材料。形成结构的方法包括在有机材料中形成开口，在开口内和有机材料上形成高k电介质材料和导电材料，然后使用化学机械抛光去除高k电介质材料和导电材料从门区域外的区域。

45. 发明申请

US20060099745A1 Method for forming integrated advanced semiconductor device using sacrificial stress layer 有权
标题翻译：使用牺牲应力层形成集成先进半导体器件的方法
公开(公告)号：US20060099745A1
公开(公告)日：2006-05-11
申请号：US10981925
申请日：2004-11-05
申请人： Ju-Wang Hsu , Ming-Huan Tsai , Chien-Hao Chen , Yi-Chun Huang
发明人： Ju-Wang Hsu , Ming-Huan Tsai , Chien-Hao Chen , Yi-Chun Huang
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823835 , H01L21/823864 , H01L21/823878 , H01L29/7843 , Y10S438/938
摘要： An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS transistors. The stressed film may be a tensile or compressive nitride film. An annealing process is carried out prior to the silicide formation process. During the annealing process, the stressed nitride film preferentially remains over either the NMOS transistors or PMOS transistors, but not both, to optimize device performance. A tensile nitride film remains over the NMOS transistors but not the PMOS transistors while a compressive nitride film remains over the PMOS transistors but not the NMOS transistors, during anneal.
摘要翻译：用于形成半导体器件的集成先进方法利用牺牲应力层作为薄膜堆叠的一部分，其能够在器件中形成空间选择性硅化物。要被硅化的器件的低电阻部分包括NMOS晶体管和PMOS晶体管。应力膜可以是拉伸或压缩氮化物膜。在硅化物形成工艺之前进行退火处理。在退火过程中，应力氮化物膜优先保留在NMOS晶体管或PMOS晶体管之上，但不能同时保持在两者上，以优化器件性能。在退火期间，拉伸氮化物膜保留在NMOS晶体管上，而不是PMOS晶体管，而压电氮化物膜保留在PMOS晶体管上，而不保留在NMOS晶体管上。

46. 发明申请

US20050212058A1 Resistance-reduced semiconductor device and fabrication thereof 审中-公开
标题翻译：电阻降低的半导体器件及其制造
公开(公告)号：US20050212058A1
公开(公告)日：2005-09-29
申请号：US10806217
申请日：2004-03-23
申请人： Yi-Chun Huang , Jyu-Horng Shieh , Ju-Wang Hsu
发明人： Yi-Chun Huang , Jyu-Horng Shieh , Ju-Wang Hsu
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/60 , H01L29/06 , H01L29/76 , H01L31/062
CPC分类号： H01L21/76897 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L29/6659
摘要： A resistance-reduced semiconductor device and fabrication thereof. The semiconductor device of the invention includes a semiconductor device body exposing at least one silicon-containing portion, a metal silicide layer with a first resistivity overlying the silicon-containing portion and a conductor layer with a second resistivity overlying the metal silicide layer, wherein the second resistivity is smaller than the first resistivity.
摘要翻译：一种电阻降低半导体器件及其制造。本发明的半导体器件包括暴露至少一个含硅部分的半导体器件本体，覆盖硅含量部分的第一电阻率的金属硅化物层和覆盖金属硅化物层的第二电阻率的导体层，其中第二电阻率小于第一电阻率。

47. 发明授权

US06838381B2 Methods for improving sheet resistance of silicide layer after removal of etch stop layer 失效
标题翻译：去除蚀刻停止层之后提高硅化物层的薄层电阻的方法
公开(公告)号：US06838381B2
公开(公告)日：2005-01-04
申请号：US10329598
申请日：2002-12-26
申请人： Peng-Fu Hsu , Ming-Huan Tsai , Baw-Ching Perng , Ju-Wang Hsu , Yaun-Hung Chiu
发明人： Peng-Fu Hsu , Ming-Huan Tsai , Baw-Ching Perng , Ju-Wang Hsu , Yaun-Hung Chiu
IPC分类号： H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/76802 , H01L21/76814 , H01L21/76829
摘要： A method of manufacturing a semiconductor device is provided. A nickel silicide layer (e.g., NiSi) is formed on a substrate. Next, a hydrogen plasma treatment may be performed on the silicide layer, which may induce the formation of metal/silicon hydride bonds in the silicide layer. An etch stop layer is formed over the silicide layer. A dielectric layer is formed over the etch stop layer. An opening is formed in the dielectric layer. A portion of the etch stop layer is etched away at the opening to expose at least a portion of the silicide layer therebeneath. The etch chemistry mixture used during the etching step preferably includes hydrogen gas. The change in sheet resistance for the exposed silicide layer portion at the opening after the etching step, as compared to before the etching step, is preferably not greater than about 0.10 ohms/square.
摘要翻译：提供一种制造半导体器件的方法。在衬底上形成硅化镍层（例如NiSi）。接下来，可以在硅化物层上进行氢等离子体处理，这可能在硅化物层中引起金属/硅氢化物键的形成。在硅化物层之上形成蚀刻停止层。在蚀刻停止层上方形成介电层。在电介质层中形成开口。蚀刻停止层的一部分在开口处被蚀刻掉以暴露其下面的硅化物层的至少一部分。在蚀刻步骤期间使用的蚀刻化学混合物优选包括氢气。与蚀刻步骤之前相比，在蚀刻步骤之后的开口处的暴露的硅化物层部分的薄层电阻的变化优选不大于约0.10欧姆/平方。

48. 发明授权

US06780782B1 Bi-level resist structure and fabrication method for contact holes on semiconductor substrates 有权
标题翻译：半导体衬底上的接触孔的双层抗蚀剂结构和制造方法
公开(公告)号：US06780782B1
公开(公告)日：2004-08-24
申请号：US10357579
申请日：2003-02-04
申请人： Ming-Huan Tsai , Hun-Jan Tao , Tsang Jiuh Wu , Ju Wang Hsu
发明人： Ming-Huan Tsai , Hun-Jan Tao , Tsang Jiuh Wu , Ju Wang Hsu
IPC分类号： H01L21302
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/31138 , H01L21/31144
摘要： An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique combination of gaseous components in a plasma etching process which is used to dry develop the bi-level resist mask as well as etch through a silicon oxide dielectric layer. The gaseous components comprise a mixture of a fluorine containing gas, such as C4F8, C5F8, C4F6, CHF3 or similar species, an inert gas, such as helium or argon, an optional weak oxidant, such as CO or O2 or similar species, and a nitrogen source, such as N2, N2O, or NH3 or similar species. The patterned masking layer can be used to reliably etch contact holes in silicon oxide layers on semiconductor substrates, where the holes have diameters of about 0.1 micron or less.
摘要翻译：已经开发了一种通过介电层蚀刻非常小的接触孔的改进方法，其用于在半导体衬底上形成的多层集成电路中分离导电层。该方法在抗蚀剂结构中使用双层ARC涂层，并且在等离子体蚀刻工艺中使用气态组分的独特组合，其用于干燥显影双电平抗蚀剂掩模以及通过氧化硅介电层进行蚀刻。气态组分包括含氟气体如C 4 F 8，C 5 F 8，C 4 F 6，CHF 3或类似物质，惰性气体如氦气或氩气，任选的弱氧化剂如CO或O 2或类似物质的混合物，以及氮源，例如N 2，N 2 O或NH 3或类似物质。图案化掩模层可用于可靠地蚀刻半导体衬底上的氧化硅层中的接触孔，其中孔的直径为约0.1微米或更小。

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