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41. 发明授权

US06784722B2 Wide-range local bias generator for body bias grid 失效
标题翻译：用于车身偏置网格的宽范围局部偏置发生器
公开(公告)号：US06784722B2
公开(公告)日：2004-08-31
申请号：US10267951
申请日：2002-10-09
申请人： Stephen H. Tang , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
发明人： Stephen H. Tang , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
IPC分类号： G35F110
CPC分类号： G05F3/205 , H03K2217/0018
摘要： A circuit is provided having a differential difference amplifier (DDA) having first and second inputs to receive a desired body bias signal, and a third input to receive a supply voltage, the DDA configured to generate an intermediate output signal, the intermediate output signal coupled to an output buffer generating an output signal having a desired gain, the DDA having a fourth input, to cause the output signal to reference to variations in the supply voltage.
摘要翻译：提供一种具有差分差分放大器（DDA）的电路，差分差分放大器（DDA）具有第一和第二输入端以接收所需的体偏置信号;以及第三输入端，用于接收电源电压，所述DDA被配置为产生中间输出信号，所述中间输出信号耦合到产生具有期望增益的输出信号的输出缓冲器，DDA具有第四输入，以使输出信号参考电源电压的变化。

42. 发明授权

US06763484B2 Body bias using scan chains 有权
标题翻译：使用扫描链的身体偏倚
公开(公告)号：US06763484B2
公开(公告)日：2004-07-13
申请号：US09894465
申请日：2001-06-28
申请人： James W. Tschanz , Siva G. Narendra , Vivek K. De
发明人： James W. Tschanz , Siva G. Narendra , Vivek K. De
IPC分类号： G01R3128
CPC分类号： G01R31/318575 , H03K2217/0018
摘要： A logic unit and method incorporating body biasing using scan chains, the logic unit comprising a functional unit block including a body and a scan chain, and a variable voltage source coupled to the scan chain to receive control signals from the scan chain and coupled to the body to provide a bias voltage to the body, and the method comprising identifying a preferred body bias voltage for a functional unit block having a body; and permanently programming a plurality of control signals coupled to a variable voltage source that provides the preferred body bias voltage to the body.
摘要翻译：一种包括使用扫描链的主体偏置的逻辑单元和方法，所述逻辑单元包括包括主体和扫描链的功能单元块，以及耦合到所述扫描链的可变电压源，以从所述扫描链接收控制信号并耦合到所述扫描链以向身体提供偏置电压，并且该方法包括识别具有身体的功能单元块的优选身体偏置电压; 并且永久地编程耦合到可变电压源的多个控制信号，所述可变电压源向身体提供优选的身体偏置电压。

43. 发明申请

US20160172036A1 MEMORY CELL WITH RETENTION USING RESISTIVE MEMORY 审中-公开
标题翻译：使用电阻记忆的记忆单元
公开(公告)号：US20160172036A1
公开(公告)日：2016-06-16
申请号：US14129676
申请日：2013-08-16
申请人： Charles AUGUSTINE , Carlos TOKUNAGA , James W. TSCHANZ
发明人： Charles AUGUSTINE , Carlos TOKUNAGA , James W. TSCHANZ
IPC分类号： G11C14/00 , G11C11/16
CPC分类号： G11C14/0081 , G11C11/1697 , G11C13/0011 , G11C14/0072 , G11C14/009
摘要： Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: a memory element including cross-coupled cells having a first node and a second node; a first transistor coupled to the first node; a second transistor coupled to the second node; and a resistive memory element coupled to the first and second transistors.
摘要翻译：描述了一种包括使用电阻性存储器保持的存储单元的装置。该装置包括：存储元件，其包括具有第一节点和第二节点的交叉耦合小区; 耦合到所述第一节点的第一晶体管; 耦合到所述第二节点的第二晶体管; 以及耦合到第一和第二晶体管的电阻性存储元件。

44. 发明申请

US20140277812A1 DUAL LOOP DIGITAL LOW DROP REGULATOR AND CURRENT SHARING CONTROL APPARATUS FOR DISTRIBUTABLE VOLTAGE REGULATORS 审中-公开
标题翻译：双环数字低电平调节器和分布式电压调节器的电流共享控制装置
公开(公告)号：US20140277812A1
公开(公告)日：2014-09-18
申请号：US13801777
申请日：2013-03-13
申请人： Yi-Chun Shih , Kaushik Mazumdar , Stephen T. Kim , Rinkle Jain , James W. Tschanz , Muhammad M. Khellah
发明人： Yi-Chun Shih , Kaushik Mazumdar , Stephen T. Kim , Rinkle Jain , James W. Tschanz , Muhammad M. Khellah
IPC分类号： G05F5/00
CPC分类号： G05F1/563 , G05F1/00 , G05F1/46 , H02M3/156
摘要： Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.
摘要翻译：描述了一种装置，其包括：耦合到输入电源和负载的多个晶体管; 第一比较器，其具有耦合到所述负载的第一节点，以及耦合到第一参考的第二节点; 第二比较器，其具有耦合到所述负载的第一节点，以及耦合到第二参考的第二节点，所述第二参考与所述第一参考不同; 以及逻辑单元，用于接收第一比较器的输出和第二比较器的输出，逻辑单元根据第一和第二比较器的输出接通或关断多个晶体管的晶体管。

45. 发明申请

US20140236582A1 LOW POWER VOICE DETECTION 有权
标题翻译：低功率语音检测
公开(公告)号：US20140236582A1
公开(公告)日：2014-08-21
申请号：US13997070
申请日：2011-12-06
申请人： Arijit Raychowdhury , Willem M. Beltman , James W. Tschanz , Carlos Tokunaga , Michael E. Deisher , Thomas E. Walsh
发明人： Arijit Raychowdhury , Willem M. Beltman , James W. Tschanz , Carlos Tokunaga , Michael E. Deisher , Thomas E. Walsh
IPC分类号： G10L15/20 , G10L21/0232 , G10L15/22 , G10L21/0208
CPC分类号： G10L15/20 , G06F1/3234 , G06F17/142 , G10L15/22 , G10L15/285 , G10L21/0208 , G10L21/0232 , G10L25/18 , G10L25/84 , G10L2015/223 , G10L2021/02087
摘要： Methods of enabling voice processing with minimal power consumption includes recording time-domain audio signal at a first clock frequency and a first voltage, and performing Fast Fourier Transform (FFT) operations on the time-domain audio signal at a second clock frequency to generate frequency-domain audio signal. The frequency domain audio signal may be enhanced to obtain better signal to noise ratio, through one or multiple filtering and enhancing techniques. The enhanced audio signal may be used to generate the total signal energy and estimate the background noise energy. Decision logic may determine from the signal energy and the background noise, the presence or absence of the human voice. The first clock frequency may be different from the second clock frequency.
摘要翻译：以最小功耗实现语音处理的方法包括以第一时钟频率和第一电压记录时域音频信号，并且以第二时钟频率对时域音频信号执行快速傅立叶变换（FFT）操作以产生频率域音频信号。可以通过一个或多个滤波和增强技术来增强频域音频信号以获得更好的信噪比。增强音频信号可用于产生总信号能量并估计背景噪声能量。决策逻辑可以根据信号能量和背景噪声来确定人类语音的存在或不存在。第一时钟频率可以不同于第二时钟频率。

46. 发明申请

US20140122947A1 Sequential Circuit with Error Detection 有权
标题翻译：具有错误检测的顺序电路
公开(公告)号：US20140122947A1
公开(公告)日：2014-05-01
申请号：US13664153
申请日：2012-10-30
申请人： Keith A. Bowman , James W. Tschanz , Nam Sung Kim , Janice C. Lee , Christopher B. Wilkerson , Shih-Lien L. Lu , Tanay Karnik , Vivek K. De
发明人： Keith A. Bowman , James W. Tschanz , Nam Sung Kim , Janice C. Lee , Christopher B. Wilkerson , Shih-Lien L. Lu , Tanay Karnik , Vivek K. De
IPC分类号： G06F1/08 , G06F11/07
CPC分类号： G01R31/3177 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G06F1/10 , G06F11/0706 , G06F11/0757 , G06F11/0793 , H03K3/0375
摘要： Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
摘要翻译：提供了具有错误检测的顺序电路。例如，它们可以用于替代传统的主从触发器，例如在关键路径电路中，以检测并启动在顺序输入处的后期转换的校正。在一些实施例中，这样的顺序可以包括具有时间借用锁存器的转换检测器。

47. 发明申请

US20140037042A1 INTEGRATED NON-VOLATILE MONOTONIC COUNTERS 有权
标题翻译：集成非易失性单体计数器
公开(公告)号：US20140037042A1
公开(公告)日：2014-02-06
申请号：US13564497
申请日：2012-08-01
申请人： James W. Tschanz , Christopher B. Wilkerson , Scott Robinson , Shih-Lien Lu
发明人： James W. Tschanz , Christopher B. Wilkerson , Scott Robinson , Shih-Lien Lu
IPC分类号： G06M3/00 , H03K21/00 , H03K21/02
CPC分类号： H03K21/023 , H03K21/12
摘要： Some embodiments include a counter having a first generator to generate signals having different frequencies, and a second generator to generate counter values of the counter. Each of the counter values may be based at least in part on a number of transitions of a respective signal among the signals. Other embodiments are described.
摘要翻译：一些实施例包括具有第一发生器以产生具有不同频率的信号的计数器，以及产生计数器的计数器值的第二发生器。每个计数器值可以至少部分地基于信号中相应信号的转换的数量。描述其他实施例。

48. 发明授权

US08288846B2 Power management integrated circuit 有权
标题翻译：电源管理集成电路
公开(公告)号：US08288846B2
公开(公告)日：2012-10-16
申请号：US12660305
申请日：2010-02-24
申请人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： H01L23/495 , H01L23/52 , H01L21/00
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。

49. 发明授权

US07444528B2 Component reliability budgeting system 有权
标题翻译：组件可靠性预算系统
公开(公告)号：US07444528B2
公开(公告)日：2008-10-28
申请号：US11295400
申请日：2005-12-06
申请人： Siva G. Narendra , James W. Tschanz , Vivek K. De , Stephen H. Tang
发明人： Siva G. Narendra , James W. Tschanz , Vivek K. De , Stephen H. Tang
IPC分类号： G06F1/26 , G06F1/00
CPC分类号： G06F1/206 , Y02D10/16
摘要： A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要翻译：系统可以包括获取表示提供给电气部件的过去电源电压的电源电压信息，基于电源电压信息获取表示电气部件的过去温度的温度信息和电气部件的性能特性的控制，以及温度信息。一些实施例还可以包括基于电源电压信息，温度信息以及电气部件的可靠性规格以及基于可靠性裕度的性能特性的改变来确定可靠性裕度。

50. 发明授权

US07397395B2 Representative majority voter for bus invert coding 有权
标题翻译：代表大多数选民为总线反转编码
公开(公告)号：US07397395B2
公开(公告)日：2008-07-08
申请号：US11059174
申请日：2005-02-16
申请人： James W Tschanz , Mircea R. Stan , Muhammad M Khellah , Yibin Ye , Vivek K De
发明人： James W Tschanz , Mircea R. Stan , Muhammad M Khellah , Yibin Ye , Vivek K De
IPC分类号： H03M7/00
CPC分类号： G06F13/4213 , H03K19/23 , H03M5/145 , Y02D10/14 , Y02D10/151
摘要： In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes a conditional inverter to apply the invert signal to the pluraility of bits.
摘要翻译：一般来说，在一个方面，本公开描述了一种包括代表性的多数选民门来分析多个位的位转换的装置。分组的分类分析。代表大多数选民门根据分析产生反转信号。该装置进一步包括条件反相器将反相信号应用于多个位。

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