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41. 发明授权

US08988093B2 Bumped semiconductor wafer or die level electrical interconnect 有权
标题翻译：凸起的半导体晶片或芯片级电气互连
公开(公告)号：US08988093B2
公开(公告)日：2015-03-24
申请号：US13413032
申请日：2012-03-06
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： G01R1/067 , G01R31/28
CPC分类号： G01R31/2889
摘要： A probe assembly that acts as a temporary interconnect between terminals on an IC device and a test station. The probe assembly includes a plurality of stud bumps arranged on a first surface of a substrate in a configuration corresponding to the terminal on the IC device. The stud bumps include a shape adapted to temporarily couple with the terminals on the IC device. A plurality of conductive traces on the substrate electrically couple the stud bumps with the test station.
摘要翻译：探针组件，用作IC器件和测试台之间的端子之间的临时互连。探针组件包括布置在基板的第一表面上的多个突起凸块，其配置对应于IC器件上的端子。螺柱凸块包括适于临时与IC器件上的端子连接的形状。基板上的多个导电迹线使柱形突起与测试台电耦合。

42. 发明授权

US08981809B2 Compliant printed circuit semiconductor tester interface 有权
标题翻译：符合印刷电路半导体测试仪接口
公开(公告)号：US08981809B2
公开(公告)日：2015-03-17
申请号：US13319203
申请日：2010-06-28
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： G01R31/02 , G01R1/04 , G01R1/073
CPC分类号： G01R1/0466 , G01R1/07314 , G01R1/0735 , G01R1/07378 , Y10T29/49155
摘要： A compliant printed circuit semiconductor tester interface that provides a temporary interconnect between terminals on integrated circuit (IC) devices being tested. The compliant printed circuit semiconductor tester interface includes at least one dielectric layer printed with recesses corresponding to a target circuit geometry. A conductive material is deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads accessible along a first surface of the compliant printed circuit. At least one dielectric covering layer is preferably applied over the circuit geometry. A plurality of openings in the dielectric covering layer are provided to permit electrical coupling of terminals on the IC device and the first contact pads. Testing electronics that to test electrical functions of the IC device are electrically coupled to the circuit geometry.
摘要翻译：一种兼容的印刷电路半导体测试器接口，其在被测试的集成电路（IC）器件上的端子之间提供临时互连。符合标准的印刷电路半导体测试器接口包括至少一个印刷有对应于目标电路几何形状的凹部的电介质层。导电材料沉积在包括电路几何形状的凹槽的至少一部分中，以及可沿柔性印刷电路的第一表面接近的多个第一接触焊盘。优选地，在电路几何形状上施加至少一个电介质覆盖层。设置电介质覆盖层中的多个开口以允许IC器件上的端子和第一接触焊盘的电耦合。用于测试IC器件的电气功能的测试电子器件电耦合到电路几何形状。

43. 发明授权

US08912812B2 Compliant printed circuit wafer probe diagnostic tool 有权
标题翻译：符合标准的印刷电路晶圆探针诊断工具
公开(公告)号：US08912812B2
公开(公告)日：2014-12-16
申请号：US13318038
申请日：2010-05-27
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： G01R31/00 , G01R31/28 , G01R31/02
CPC分类号： G01R31/2889 , G01R31/024 , H01L2224/16225
摘要： Diagnostic tools for testing wafer-level IC devices, and a method of making the same. The first diagnostic tool can include a first compliant printed circuit with a plurality of contact pads configured to form an electrical interconnect at a first interface between distal ends of probe members in the wafer probe and contact pads on a wafer-level IC device. A plurality of printed conductive traces electrically couple to a plurality of the contact pads on the first compliant printed circuit. A plurality of electrical devices are printed on the first compliant printed circuit at a location away from the first interface. The electrical devices are electrically coupled to the conductive traces and are configured to provide one or more of continuity testing or functionality of the wafer-level IC devices. A second diagnostic tool includes a second compliant printed circuit electrically coupled to a dedicated IC testing device. A plurality of electrical devices are printed on the second compliant printed circuit and electrically coupled to the dedicated IC device.
摘要翻译：用于测试晶圆级IC器件的诊断工具及其制作方法。第一诊断工具可以包括具有多个接触焊盘的第一顺应印刷电路，其被配置为在晶片探针中的探针部件的远端和晶片级IC器件上的接触焊盘之间的第一接口处形成电互连。多个印刷导电迹线电耦合到第一顺应印刷电路上的多个接触焊盘。在远离第一接口的位置处，在第一顺应印刷电路上印刷多个电气设备。电气设备电耦合到导电迹线并且被配置为提供晶片级IC器件的连续性测试或功能的一个或多个。第二诊断工具包括电耦合到专用IC测试装置的第二顺应印刷电路。多个电气设备印刷在第二顺应印刷电路上并电耦合到专用IC器件。

44. 发明授权

US08789272B2 Method of making a compliant printed circuit peripheral lead semiconductor test socket 有权
标题翻译：制造兼容印刷电路外围引线半导体测试插座的方法
公开(公告)号：US08789272B2
公开(公告)日：2014-07-29
申请号：US13318171
申请日：2010-05-27
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H05K3/02 , H05K3/10
CPC分类号： G01R1/0483 , G01R1/0466 , H05K7/1061
摘要： A test socket that provides a temporary interconnect between terminals on an integrated circuit (IC) device and contact pads on a test printed circuit board (PCB). The test socket includes a compliant printed circuit and a socket housing. The compliant printed circuit includes at least one compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of conductive traces electrically coupling the first and second contact members. The compliant layer is positioned to bias the first contact members against the terminals on the IC device and the second contact members against contact pads on the test PCB. The socket housing is coupled to the compliant printed circuit so the first contact members are positioned in a recess of the socket housing sized to receive the IC device.
摘要翻译：一个测试插座，用于在集成电路（IC）器件的端子和测试印刷电路板（PCB）上的接触焊盘之间提供临时互连。测试插座包括兼容印刷电路和插座外壳。柔性印刷电路包括至少一个柔性层，沿着第一主表面定位的多个第一接触构件，沿第二主表面定位的多个第二接触构件以及将第一和第二接触电耦合的多个导电迹线会员柔性层被定位成将第一接触构件抵靠在IC器件上的端子上，并且第二接触构件抵抗测试PCB上的接触焊盘。插座壳体耦合到柔性印刷电路，使得第一接触构件位于插座壳体的凹部中，其尺寸设置成接收IC器件。

45. 发明申请

US20140192498A1 DIRECT METALIZATION OF ELECTRICAL CIRCUIT STRUCTURES 有权
标题翻译：电气电路结构的直接金属化
公开(公告)号：US20140192498A1
公开(公告)日：2014-07-10
申请号：US14238638
申请日：2012-09-06
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H05K1/11 , H01L23/498 , H05K3/46
CPC分类号： H05K1/115 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L24/16 , H01L24/48 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/12041 , H01L2924/12042 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K3/4688 , Y10T29/49117 , H01L2224/45099 , H01L2924/00
摘要： An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is plated on surfaces of a plurality of the first recesses to form a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A filler material is deposited in the first conductive structures. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive structures. A conductive material is plated on surfaces of a plurality of the second recesses to form a plurality of second conductive structures electrically coupled to, and extending parallel to the first conductive structures.
摘要翻译：一种电互连，包括具有第一表面和第二表面的第一电路层。至少第一电介质层印刷在第一电路层的第一表面上以包括多个第一凹槽。导电材料被电镀在多个第一凹槽的表面上，以形成多个第一导电结构，该第一导电结构与第一电路层电耦合并大致垂直于第一电路层延伸。填料材料沉积在第一导电结构中。至少第二电介质层被印刷在第一电介质层上以包括与多个第一导电结构大致对准的多个第二凹槽。导电材料被镀在多个第二凹槽的表面上以形成电耦合到第一导电结构并平行于第一导电结构延伸的多个第二导电结构。

46. 发明授权

US08758067B2 Selective metalization of electrical connector or socket housing 有权
标题翻译：电连接器或插座外壳的选择性金属化
公开(公告)号：US08758067B2
公开(公告)日：2014-06-24
申请号：US13412870
申请日：2012-03-06
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H01R13/24
CPC分类号： H01R12/57 , H01R12/52 , H01R12/523 , H01R12/716 , H01R13/2421 , H05K1/023 , H05K1/141 , H05K1/16 , H05K3/4007 , H05K2201/10378 , Y10T29/49204
摘要： A electrical interconnect adapted to provide an interface between contact pads on an IC device and a PCB. The electrical interconnect includes a multi-layered substrate with a first surface with a plurality of first openings having first cross-sections, a second surface with a plurality of second openings having second cross-sections, and center openings connecting the first and second openings. The center openings include at least one cross-section greater than the first and second cross-sections. A plurality of spring probe contact members are located in the center openings. The contact members include first contact tips extending through the first opening and above the first surface, second contact tips extending through the second openings and above the second surface, and center portions located in the center openings. The center portions include a shape adapted to bias the first and second contact tips toward the IC device and PCB, respectively. A dielectric material different from the material of the substrate is located in at least one of the first opening, the second opening, or the center opening.
摘要翻译：适于提供IC器件上的接触焊盘和PCB之间的接口的电互连。电互连包括具有第一表面的多层基底，第一表面具有多个具有第一横截面的第一开口，具有多个具有第二横截面的第二开口的第二表面和连接第一和第二开口的中心孔。中心开口包括大于第一和第二横截面的至少一个横截面。多个弹簧探针接触构件位于中心开口中。接触构件包括延伸穿过第一开口并在第一表面上方的第一接触尖端，延伸穿过第二开口并位于第二表面上方的第二接触末端以及位于中心开口中的中心部分。中心部分包括适于分别朝向IC器件和PCB偏置第一和第二接触尖端的形状。与基板的材料不同的介电材料位于第一开口，第二开口或中心开口中的至少一个中。

47. 发明申请

US20130223034A1 HIGH PERFORMANCE ELECTRICAL CIRCUIT STRUCTURE 有权
标题翻译：高性能电路结构
公开(公告)号：US20130223034A1
公开(公告)日：2013-08-29
申请号：US13879783
申请日：2011-10-18
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H05K1/18 , H05K3/12 , H05K3/30 , H05K1/11 , H05K1/16
CPC分类号： H05K1/18 , H01L23/49811 , H01L23/5383 , H01L2224/16 , H01L2924/09701 , H01L2924/12044 , H05K1/0274 , H05K1/111 , H05K1/115 , H05K1/16 , H05K3/1291 , H05K3/30 , H05K3/325 , H05K3/4007 , H05K3/4664 , H05K2201/0133 , Y10T29/49155
摘要： A high performance electrical interconnect adapted to provide an interface between terminals on first and second circuit members. The electrical interconnect includes a first circuitry layer with a first surface and a second surface having a plurality of contact pads adapted to electrically coupled with the terminals on the first circuit member. At least one dielectric layer is printed on the first surface of the first circuitry layer. The dielectric layer includes a plurality recesses. A conductive material is deposited in at least a portion of the recesses to create circuit geometry electrically coupled with the first circuitry layer. A second circuitry layer includes a first surface a plurality of contact pads adapted to electrically couple with the terminals on the second circuit member and a second surface attached to the dielectric layers. The circuit geometry electrically couples the first circuitry layer to the second circuitry layer.
摘要翻译：一种适用于在第一和第二电路构件上的端子之间提供接口的高性能电互连。电互连包括具有第一表面的第一电路层和具有适于与第一电路构件上的端子电耦合的多个接触焊盘的第二表面。至少一个电介质层被印刷在第一电路层的第一表面上。电介质层包括多个凹部。导电材料沉积在凹陷的至少一部分中以产生与第一电路层电耦合的电路几何形状。第二电路层包括第一表面，多个接触焊盘，其适于与第二电路部件上的端子电耦合，以及附接到电介质层的第二表面。电路几何电耦合第一电路层到第二电路层。

48. 发明申请

US20130210276A1 ELECTRICAL INTERCONNECT IC DEVICE SOCKET 有权
标题翻译：电气互连IC器件插座
公开(公告)号：US20130210276A1
公开(公告)日：2013-08-15
申请号：US13880231
申请日：2011-11-29
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H01R12/70 , H01R43/00
CPC分类号： H01R12/7082 , H01R11/16 , H01R12/714 , H01R13/24 , H01R43/00 , H05K7/1061 , Y10T29/49208
摘要： A surface mount electrical interconnect adapted to provide an interface between contact pads on an LGA device and a PCB. The electrical interconnect includes a socket substrate having a first surface with a plurality of first openings having first cross-sections, a second surface with a plurality of second openings having second cross-sections, and center openings connecting the first and second openings. The center openings include at least one cross-section greater than the first and second cross-sections. A plurality of contact members are located in the socket substrate such that first contact tips are located proximate the first openings, second contact tips are located proximate the second openings, and center portions located in the center openings.
摘要翻译：适于在LGA器件和PCB之间提供接触焊盘之间的接口的表面贴装电互连。电互连包括具有第一表面的插座衬底，第一表面具有多个具有第一横截面的第一开口，具有多个具有第二横截面的第二开口的第二表面和连接第一和第二开口的中心开口。中心开口包括大于第一和第二横截面的至少一个横截面。多个接触构件位于插座衬底中，使得第一接触尖端位于第一开口附近，第二接触尖端位于第二开口附近，中心部分位于中心开口中。

49. 发明申请

US20130105984A1 SEMICONDUCTOR DEVICE PACKAGE ADAPTER 有权
标题翻译：半导体器件封装适配器
公开(公告)号：US20130105984A1
公开(公告)日：2013-05-02
申请号：US13643436
申请日：2011-04-25
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H01L23/00
CPC分类号： H01L24/14 , H01L23/552 , H01L24/19 , H01L24/20 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/04105 , H01L2924/01029 , H01L2924/10253 , H01L2924/12042 , H01L2924/1306 , H01L2924/14 , H01R12/7076 , H01R13/6474 , H01R13/6585 , H01R2201/20 , H05K3/32 , H05K3/3436 , H05K2201/10378 , H05K2201/1059 , H05K2201/10734 , H05K2201/10962 , H01L2924/00
摘要： A semiconductor device packaged adapter for electrically coupling contacts on a first circuit member to contacts on a second circuit member. The adapter typically includes first and second substrates, each with arrays of terminals. Proximal ends of the first terminals on the first substrate are arranged to be soldered to the contacts on the first circuit member and proximal ends of the) second terminals on the second substrate are arranged to be soldered to the contacts on the second circuit member. Complementary engaging structures located on distal ends of the first and second terminals engage to electrically and mechanically couple the first circuit member to the second circuit member.
摘要翻译：一种半导体器件封装适配器，用于将第一电路构件上的触点电耦合到第二电路构件上的触点。适配器通常包括第一和第二基板，每个具有端子阵列。第一基板上的第一端子的近端布置成被焊接到第一电路构件上的触点，并且第二基板上的第二端子的近端布置成焊接到第二电路构件上的触点。位于第一和第二端子的远端上的互补接合结构接合以将第一电路构件电连接和机械耦合到第二电路构件。

50. 发明申请

US20130078860A1 ELECTRICAL CONNECTOR INSULATOR HOUSING 有权
标题翻译：电气连接器绝缘体外壳
公开(公告)号：US20130078860A1
公开(公告)日：2013-03-28
申请号：US13700639
申请日：2011-06-02
申请人： James Rathburn
发明人： James Rathburn
IPC分类号： H01R13/24 , H01R43/20 , H01R13/66
CPC分类号： H01R13/24 , H01R12/52 , H01R12/7082 , H01R13/2421 , H01R13/66 , H01R43/20 , H05K3/361 , H05K3/368 , H05K7/1069 , H05K2201/0187 , H05K2201/10378 , Y10T29/4922
摘要： A socket housing and method of making the socket housing. A plurality of dielectric layers are printed with a plurality of recesses on a substrate. The dielectric layers include at least two different dielectric materials. A sacrificial material is printed ted in the recesses. The assembly is removed from the substrate and the sacrificial material is removed from the recesses. At least one contact member is located in a plurality of the recesses. Distal ends of the contact members are adapted to electrically couple with circuit members.
摘要翻译：插座壳体和制造插座壳体的方法。多个电介质层在衬底上印有多个凹槽。电介质层包括至少两种不同的介电材料。牺牲材料印在凹槽中。将组件从衬底移除，并且牺牲材料从凹部移除。至少一个接触构件位于多个凹部中。接触构件的远端适于与电路构件电耦合。

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