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41. 发明授权

US06487712B1 Method of manufacturing mask for conductive wirings in semiconductor device 失效
标题翻译：制造半导体器件中导电布线掩模的方法
公开(公告)号：US06487712B1
公开(公告)日：2002-11-26
申请号：US09695153
申请日：2000-10-24
申请人： Jae Kap Kim
发明人： Jae Kap Kim
IPC分类号： G06F1750
CPC分类号： G03F1/36 , H01L21/31053 , H01L21/76819 , H01L21/76838
摘要： Disclosed is a method of manufacturing a mask for conductive wirings in a semiconductor device, wherein the conductive wirings are formed on a semiconductor substrate of the semiconductor device, comprising the steps of: (a) calculating data for the entire regions of the semiconductor substrate on which the conductive wirings are formed; (b) reading the size, shape and position of the conductive wiring patterns for the conductive wirings to generate data for conductive wirings, and storing the generated conductive wirings data; (c) extending the conductive wirings data by a predetermined size to generate data for the extended conductive wirings; (d) subtracting the extended conductive wirings data from the data for the entire regions of the semiconductor substrate to calculate a differential data between the extended conductive wirings data and the entire regions data, and to generate data for dummy conductive wiring pattern; (e) adding the conductive wirings data to the dummy conductive wiring pattern data to form a pattern the size and position of which correspond to data obtained by the addition operation on the mask by using a clear field method.
摘要翻译：公开了一种在半导体器件中制造用于导电布线的掩模的方法，其中导电布线形成在半导体器件的半导体衬底上，包括以下步骤：（a）计算半导体衬底的整个区域的数据，导电布线形成; （b）读取用于导电布线的导电布线图形的尺寸，形状和位置，以生成用于导电布线的数据，并存储所生成的导电布线数据; （c）将导电布线数据延伸预定尺寸以产生用于扩展导电布线的数据; （d）从半导体衬底的整个区域的数据中减去扩展导电布线数据，以计算扩展导电布线数据与整个区域数据之间的差分数据，并生成用于虚拟导电布线图案的数据; （e）将导电布线数据添加到虚拟导电布线图案数据，以通过使用清晰的场方法形成其尺寸和位置对应于通过掩模上的加法运算获得的数据的图案。

42. 发明授权

US06376307B1 Method for fabricating NOR type memory cells of nonvolatile memory device 失效
标题翻译：用于制造非易失性存储器件的NOR型存储单元的方法
公开(公告)号：US06376307B1
公开(公告)日：2002-04-23
申请号：US09684669
申请日：2000-10-06
申请人： Jae Kap Kim
发明人： Jae Kap Kim
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for fabricating NOR type memory cells of a nonvolatile memory device, floating gate insulating film, a floating gate electrode, a control gate insulating film, a control gate electrode, and an insulating film sequentially stacked in the shape of pattern on each of memory cell regions of a semiconductor substrate defined by an isolation film are formed; a source electrode and a drain electrode are formed in portions of the semiconductor substrate exposed at both sides of the gate electrode, a first etching barrier film is formed on the resultant; a first interlayer insulating film is formed on the first etching barrier film in a planarized fashion; a desired portion of the first interlayer insulating film is etched to form a first contact hole exposing the source and drain electrodes; a first conductive film in a planarized fashion is formed on the resultant to bury the first contact hole; the first conductive film is etched to form a source electrode line contacting the source electrode and a contact plug contacting the drain electrode; a second etching barrier film is formed on the resultant; a second interlayer insulating film is formed in a planarized fashion on the second etching barrier film; a desired portion of the second insulating film is etched to form second contact hole exposing the contact plug; and a bit line connected to the contact plug is formed via the second contact hole on the second interlayer insulating film.
摘要翻译：一种用于制造非易失性存储器件，浮栅绝缘膜，浮栅电极，控制栅极绝缘膜，控制栅电极和绝缘膜的NOR型存储单元的方法，所述非易失性存储器件依次以每个存储器上的图案形式堆叠形成由隔离膜限定的半导体衬底的单元区域; 源极电极和漏电极形成在半导体衬底的在栅电极的两侧露出的部分中，在其上形成第一蚀刻阻挡膜; 在第一蚀刻阻挡膜上以平面化方式形成第一层间绝缘膜; 蚀刻第一层间绝缘膜的期望部分以形成暴露源极和漏极的第一接触孔; 在第一接触孔上形成平面化的第一导电膜，蚀刻第一导电膜以形成接触源电极的源电极线和与漏电极接触的接触插塞; 在所得物上形成第二蚀刻阻挡膜; 在第二蚀刻阻挡膜上以平面形式形成第二层间绝缘膜; 蚀刻第二绝缘膜的期望部分以形成暴露接触插塞的第二接触孔; 并且通过第二层间绝缘膜上的第二接触孔形成连接到接触插塞的位线。

43. 发明授权

US06372571B1 Method of manufacturing semiconductor device 有权
公开(公告)号：US06372571B1
公开(公告)日：2002-04-16
申请号：US09747555
申请日：2000-12-22
申请人： Jae Kap Kim
发明人： Jae Kap Kim
IPC分类号： H01L218242
摘要： Provided is a method of manufacturing a semiconductor device having a stacked capacitor configured to reduce a step difference between a memory cell region and a logic circuit region adjacent thereto. In the method of manufacturing a semiconductor device, a sacrificial film removed after formation of the semiconductor device having a stacked capacitor, is preserved in the logic circuit region to be used as an interlayer insulating film. Thus, a step difference between a memory cell region having the capacitor and a logic circuit region, is removed, thereby facilitating formation of multi-layered interconnection wirings formed after forming the capacitor, and attaining fineness of the interconnection wirings.

44. 发明授权

US06339240B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06339240B1
公开(公告)日：2002-01-15
申请号：US09642379
申请日：2000-08-21
申请人： Jae Kap Kim
发明人： Jae Kap Kim
IPC分类号： H01L27108
CPC分类号： G11C11/405 , H01L27/108 , Y10S257/903 , Y10S257/904 , Y10S257/908
摘要： In DRAM comprising a read pass transistor, a write pass transistor and a storage transistor, a depletion transistor is connected to a source of the storage transistor. On a part of the source and drain of the depletion transistor, by forming an impurity region of same conductivity as that of the substrate on which the transistors are formed, a substrate voltage applied to the substrate is supplied to the storage transistor through the depletion transistor. An additional metal wire for connecting the source of the storage transistor to Vss voltage (ground voltage or substrate voltage) terminal and a contact hole area for such metal wire are not required. Accordingly, a high integration of the semiconductor can be accomplished and a reduction of reliability thereof can be decreased.
摘要翻译：在包括读传输晶体管，写通晶体管和存储晶体管的DRAM中，耗尽晶体管连接到存储晶体管的源极。在耗尽晶体管的源极和漏极的一部分上，通过形成与其上形成晶体管的衬底相同导电性的杂质区，施加到衬底的衬底电压通过耗尽晶体管提供给存储晶体管。不需要用于将存储晶体管的源极连接到Vss电压（接地电压或衬底电压）端子的附加金属线和用于这种金属线的接触孔区域。因此，可以实现半导体的高集成度并且可以降低其可靠性。

45. 发明授权

US06204538B1 SRAM cell 有权
标题翻译： SRAM单元
公开(公告)号：US06204538B1
公开(公告)日：2001-03-20
申请号：US09232869
申请日：1999-01-15
申请人： Jae-Kap Kim
发明人： Jae-Kap Kim
IPC分类号： H01L2976
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104 , Y10S257/903
摘要： The present invention discloses a static random access memory cell having a reduced cell size and method of manufacturing the same. According to the invention, the SRAM cell includes: a word line and a bit line; an access device connected to the word and bit lines, wherein in case that the word line is selected, the access device outputs data inputted from the bit line; a pull-up device connected to the access device as well as to a predetermined power voltage, wherein the pull-up device operates in pull-up manner according to the data inputted from the access device; and a pull-down device connected to the access device and the pull-up device as well as to a ground, wherein the pull-down device operates in pull-down manner according to the data inputted from the access devices.
摘要翻译：本发明公开了具有减小的单元尺寸的静态随机存取存储单元及其制造方法。根据本发明，SRAM单元包括：字线和位线; 连接到字线和位线的存取装置，其中在选择字线的情况下，存取装置输出从位线输入的数据; 连接到接入设备的上拉设备以及预定的电源电压，其中上拉设备根据从接入设备输入的数据以上拉的方式工作; 以及连接到接入设备和上拉设备以及接地的下拉设备，其中下拉设备根据从接入设备输入的数据以下拉方式工作。

46. 发明授权

US6037203A Method of fabricating a semiconductor device having triple well structure 有权
标题翻译：制造具有三重阱结构的半导体器件的方法
公开(公告)号：US6037203A
公开(公告)日：2000-03-14
申请号：US265545
申请日：1999-03-08
申请人： Jae-Kap Kim
发明人： Jae-Kap Kim
IPC分类号： H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/76 , H01L29/94
CPC分类号： H01L27/088 , H01L27/0922
摘要： The present invention discloses a semiconductor device having a triple well structure. The semiconductor device includes a N-type impurity doped buried layer, formed in the semiconductor substrate at a predetermined depth from the surface of the first active region; a first P-type well region formed beneath the second active region which is adjacent to the first active region; a second P-type well region formed in the semiconductor substrate to a depth from the surface of the first active region; a first N-type well region formed beneath the third active region; a second N-type well region formed beneath selected portion of the isolation film defining first active region and the second active region; and a first P-type doping region and a second N-type doping region formed respectively right beneath the surface of the first active region and right beneath the surface of the second active region, wherein the dopant concentration of the first doping region is lower than that of the second doping region.
摘要翻译：本发明公开了一种具有三重阱结构的半导体器件。半导体器件包括：N型杂质掺杂掩埋层，形成在距离第一有源区的表面预定深度的半导体衬底中; 形成在与所述第一有源区相邻的所述第二有源区下方的第一P型阱区; 形成在所述半导体衬底中从所述第一有源区的表面的深度的第二P型阱区; 形成在第三有源区下面的第一N型阱区; 形成在所述隔离膜的选定部分下方限定第一有源区和所述第二有源区的第二N型阱区; 以及分别在第一有源区的表面正下方形成的第二P型掺杂区和第二N型掺杂区，并且紧邻第二有源区的表面，其中第一掺杂区的掺杂浓度低于第二掺杂区域。

47. 发明授权

US6022765A Semiconductor device having a SOI structure and a manufacturing method thereof 有权
标题翻译：一种具有SOI结构的半导体器件的制造方法，其具有通过绝缘体形成的衬底偏压并与一个有源扩散层接触
公开(公告)号：US6022765A
公开(公告)日：2000-02-08
申请号：US318341
申请日：1999-05-25
申请人： Jae-Kap Kim
发明人： Jae-Kap Kim
IPC分类号： H01L29/78 , H01L21/20 , H01L21/336 , H01L21/74 , H01L21/768 , H01L27/12 , H01L29/786 , H01L21/00
CPC分类号： H01L21/743 , H01L21/768 , H01L27/1203 , H01L29/66772 , H01L29/78639 , Y10S257/901
摘要： Disclosed is a semiconductor device having a silicon on insulator structure capable of achieving a high integration, and a manufacturing method of the same. The semiconductor device includes a semiconductor substrate having a silicon on insulator structure, in which a insulating layer and a semiconductor layer are formed on a semiconductor wafer in sequence. A gate insulating film and a gate are formed on the semiconductor layer. A first impurity diffusion region and a second impurity diffusion region are formed in the semiconductor layer at both sides of the gate. A intermediate insulating layer having a first contact hole for exposing a predetermined portion of the first impurity diffusion region and a second contact hole for exposing a predetermined portion of the second impurity diffusion region and a predetermined portion of the water, is formed on an overall surface of the substrate. A first interconnection layer is electrically connected with the first impurity diffusion region through the first contact hole, and a second interconnection layer is electrically connected with the second impurity diffusion region and the predetermined portion of the wafer through the second contact hole.
摘要翻译：公开了具有能够实现高集成度的绝缘体上硅结构的半导体器件及其制造方法。半导体器件包括依次在半导体晶片上形成绝缘层和半导体层的绝缘体上结构的半导体衬底。在半导体层上形成栅极绝缘膜和栅极。在栅极两侧的半导体层中形成第一杂质扩散区和第二杂质扩散区。具有用于暴露第一杂质扩散区域的预定部分的第一接触孔和用于暴露第二杂质扩散区域的预定部分和预定部分水的第二接触孔的中间绝缘层形成在整个表面上的基底。第一互连层通过第一接触孔与第一杂质扩散区电连接，第二互连层通过第二接触孔与第二杂质扩散区和晶片的预定部分电连接。

48. 发明授权

US5753534A Semiconductor connecting device and method for making the same 失效
标题翻译：半导体连接装置及其制造方法
公开(公告)号：US5753534A
公开(公告)日：1998-05-19
申请号：US634377
申请日：1996-04-18
申请人： Jae Kap Kim
发明人： Jae Kap Kim
IPC分类号： H01L21/3213 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L23/485 , H01L23/522 , H01L27/04 , H01L27/10 , H01L27/108 , H01L21/441
CPC分类号： H01L23/485 , H01L27/10852 , H01L2924/0002
摘要： The semiconductor connecting device comprises a first conductive layer to be connected electrically; an insulating film covering the first conductive layer in such a way as to expose a predetermined portion of the first conductive layer, resulting in forming a contact hole; a conductive material pad formed in the contact hole so as to be connected with the first conductive layer, extending in a limited way over the upper surface of the insulating film; a second conductive layer formed on the extended conductive material pad, being connected with the first conductive layer; an etching barrier material formed on said conductive material pad of said contact hole and a part of the extending region, said second conductive layer being formed on the region both of said conductive material pad which is not covered with said etching barrier material and which is covered by said etching barrier material.
摘要翻译：半导体连接装置包括要电连接的第一导电层; 覆盖所述第一导电层的绝缘膜，以暴露所述第一导电层的预定部分，导致形成接触孔; 导电材料焊盘，形成在所述接触孔中，以与所述第一导电层连接，在所述绝缘膜的上表面上以有限的方式延伸; 形成在所述延伸的导电材料垫上的与所述第一导电层连接的第二导电层; 形成在所述接触孔的所述导电材料焊盘和所述延伸区域的一部分上的蚀刻阻挡材料，所述第二导电层形成在所述导电材料焊盘的两个未被所述蚀刻阻挡材料覆盖并被覆盖的区域上通过所述蚀刻阻挡材料。

49. 发明授权

US5403767A Methods for manufacturing a storage electrode of DRAM cells 失效
公开(公告)号：US5403767A
公开(公告)日：1995-04-04
申请号：US998512
申请日：1992-12-30
申请人： Jae-Kap Kim
发明人： Jae-Kap Kim
IPC分类号： H01L21/28 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817
摘要： A method for manufacturing a storage electrode of DRAM cells having a higher degree of integration in which the space between neighboring storage electrodes is made narrower than that obtainable by conventional lithographic techniques. The storage electrode is formed with a cylindrical, dual cylindrical, or jar-shaped structure to obtain a large surface area, and thus a high-capacitance.

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