会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 41. 发明申请
    • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    • 半导体器件及其制造方法
    • US20100140710A1
    • 2010-06-10
    • US12630396
    • 2009-12-03
    • Hideaki Kuroda
    • Hideaki Kuroda
    • H01L27/12H01L21/86
    • H01L21/84H01L27/105H01L27/11H01L27/1116H01L27/12H01L29/78648
    • A semiconductor device includes: a semiconductor layer; an element isolation region formed in the semiconductor layer for separation between a memory element part and a logic element part; first and second field-effect transistors formed in the memory element part and having first and second gate electrodes on a first surface side of the semiconductor layer and a second surface side opposite to the first surface, respectively, and having a source and drain region in common with each other; a third field-effect transistor formed in the logic element part and having a third gate electrode on the second surface side; and first and second insulating films formed on the semiconductor layer to cover the first field-effect transistor and the second and third field-effect transistors, respectively. The first field-effect transistor and the second field-effect transistor are fully-depleted field-effect transistors. The first gate electrode and the second gate electrode are electrically connected.
    • 半导体器件包括:半导体层; 形成在所述半导体层中用于在存储元件部分和逻辑元件部分之间分离的元件隔离区; 第一和第二场效应晶体管形成在存储元件部分中,并且在半导体层的第一表面侧上分别具有第一和第二栅极电极以及与第一表面相对的第二表面侧,并且具有源极和漏极区域 相互共同; 形成在所述逻辑元件部分中并且在所述第二表面侧上具有第三栅电极的第三场效应晶体管; 以及形成在所述半导体层上以分别覆盖所述第一场效应晶体管和所述第二和第三场效应晶体管的第一和第二绝缘膜。 第一场效应晶体管和第二场效应晶体管是完全耗尽的场效应晶体管。 第一栅电极和第二栅极电连接。
    • 46. 发明授权
    • Method of fabricating a semiconductor DRAM
    • 制造半导体DRAM的方法
    • US5374579A
    • 1994-12-20
    • US108518
    • 1993-08-18
    • Hideaki Kuroda
    • Hideaki Kuroda
    • H01L27/04H01L21/822H01L21/8242H01L27/10H01L27/108H01L21/70
    • H01L27/10852
    • A semiconductor DRAM comprises: a stacked capacitor (41) comprising a storage node electrode (42) a capacitor dielectric film (44) and a plate electrode (43), and formed in a memory cell area of a semiconductor substrate (11); and bit lines (18). A plate electrode forming film (53) having a portion extending over the entire memory cell area (21) or at least over an area including the plate electrode (43) and bit contact forming portions (24) in the memory cell area (21), and contact forming portions (34) in the peripheral circuit area (31) is formed, a second layer insulating film (15) is formed over the plate electrode forming film (53), bit contact holes (25) and contact holes (36) are formed respectively in the bit contact forming portions (24) and the contact forming portions (31) through the plate electrode forming film (53), the side surfaces of the bit contact holes (25) and the contact holes (36) are coated respectively with insulating films (26, 37), conductive plugs (16, 17) are formed in the bit contact holes (25) and the contact holes (36), and bit lines (18) are formed on the second layer insulating film (15) so as to be connected to the conductive plugs (16, 17).
    • 半导体DRAM包括:层叠电容器(41),包括存储节点电极(42),电容器电介质膜(44)和平板电极(43),并形成在半导体衬底(11)的存储单元区域中。 和位线(18)。 一种板状电极形成膜(53),其具有在整个存储单元区域(21)上延伸的部分或至少包括存储单元区域(21)中的板状电极(43)和位触点形成部分(24)的区域, 在外围电路区域(31)中形成接触形成部(34),在平板电极形成膜(53)上形成第二层绝缘膜(15),钻头接触孔(25)和接触孔 )分别通过平板电极形成膜(53)分别形成在位接触形成部分(24)和接触形成部分(31)中,钻头接触孔(25)和接触孔(36)的侧表面是 分别涂覆有绝缘膜(26,37)的导电插塞(16,17)形成在钻头接触孔(25)和接触孔(36)中,位线(18)形成在第二层绝缘膜 (15),以便连接到导电塞(16,17)。
    • 48. 发明申请
    • SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
    • 半导体器件制造方法和半导体器件
    • US20120273887A1
    • 2012-11-01
    • US13544036
    • 2012-07-09
    • Hideaki KURODA
    • Hideaki KURODA
    • H01L27/12
    • H01L27/105H01L21/84H01L22/14H01L22/20H01L27/11H01L27/1104H01L27/1116H01L27/1203H01L29/78H01L29/7855
    • A semiconductor device including a transistor formed on a first surface of a silicon layer; a first insulating film formed on the first surface of said silicon layer and covering said transistor; a wiring section formed in the first insulating film and electrically connected to the transistor; a supporting substrate formed on a surface of the first insulating film with a second insulating film interposed between the supporting substrate and the first insulating film; and an adjusting insulating film for adjusting a threshold voltage of said transistor, the adjusting insulating film being formed on a second surface of said silicon layer opposing the first surface of said silicon layer. Some embodiments may include a probing electrode electrically connected to the transistor and an opening in the silicon layer for exposing the probing electrode.
    • 一种半导体器件,包括形成在硅层的第一表面上的晶体管; 形成在所述硅层的第一表面上并覆盖所述晶体管的第一绝缘膜; 形成在第一绝缘膜中并与晶体管电连接的布线部分; 支撑基板,形成在第一绝缘膜的表面上,第二绝缘膜介于支撑基板和第一绝缘膜之间; 以及用于调节所述晶体管的阈值电压的调整绝缘膜,所述调整绝缘膜形成在所述硅层的与所述硅层的第一表面相对的第二表面上。 一些实施例可以包括电连接到晶体管的探测电极和用于暴露探测电极的硅层中的开口。
    • 49. 发明授权
    • Semiconductor device manufacturing method and semiconductor device
    • 半导体器件制造方法和半导体器件
    • US08227317B2
    • 2012-07-24
    • US12629150
    • 2009-12-02
    • Hideaki Kuroda
    • Hideaki Kuroda
    • H01L21/336
    • H01L27/105H01L21/84H01L22/14H01L22/20H01L27/11H01L27/1104H01L27/1116H01L27/1203H01L29/78H01L29/7855
    • A semiconductor device manufacturing method includes the steps of: forming a transistor on a surface side of a silicon layer of a silicon-on-insulator substrate, the silicon-on-insulator substrate being formed by laminating a substrate, an insulating layer, and the silicon layer; forming a first insulating film covering the transistor and a wiring section including a part electrically connected to the transistor on the silicon-on-insulator substrate; measuring a threshold voltage of the transistor through the wiring section; forming a supporting substrate on a surface of the first insulating film with a second insulating film interposed between the supporting substrate and the first insulating film; removing at least a part of the substrate and the insulating layer on a back side of the silicon-on-insulator substrate; and adjusting the threshold voltage of the transistor on a basis of the measured threshold voltage.
    • 半导体器件制造方法包括以下步骤:在绝缘体上硅衬底的硅层的表面侧上形成晶体管,绝缘体上硅衬底通过层叠衬底,绝缘层和 硅层; 形成覆盖晶体管的第一绝缘膜和包括与绝缘体上硅基板上的晶体管电连接的部分的布线部分; 通过所述布线部分测量所述晶体管的阈值电压; 在所述第一绝缘膜的表面上形成支撑衬底,其中所述第二绝缘膜置于所述支撑衬底和所述第一绝缘膜之间; 在绝缘体上硅衬底的背面去除衬底和绝缘层的至少一部分; 以及基于测量的阈值电压来调整晶体管的阈值电压。