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41. 发明申请

US20060081898A1 Enhanced color image sensor device and method of making the same 有权
标题翻译：增强彩色图像传感器装置及其制作方法
公开(公告)号：US20060081898A1
公开(公告)日：2006-04-20
申请号：US10966641
申请日：2004-10-15
申请人： Wen-De Wang , Dun-Nian Yaung , Tzu-Hsuan Hsu
发明人： Wen-De Wang , Dun-Nian Yaung , Tzu-Hsuan Hsu
IPC分类号： H01L31/113
CPC分类号： H01L27/14621 , H01L27/14623
摘要： A semiconductor device including a substrate having a plurality of image sensing elements formed therein, a plurality of spaced apart color filters overlying the substrate and a light blocking material interposed between adjacent spaced apart color filters.
摘要翻译：一种半导体器件，包括其上形成有多个图像感测元件的衬底，覆盖在衬底上的多个间隔开的滤色器以及插入在相邻间隔开的滤色器之间的遮光材料。

42. 发明申请

US20060057765A1 Image sensor including multiple lenses and method of manufacture thereof 审中-公开
标题翻译：包括多个透镜的图像传感器及其制造方法
公开(公告)号：US20060057765A1
公开(公告)日：2006-03-16
申请号：US10939894
申请日：2004-09-13
申请人： Tzu-Hsuan Hsu , Dun-Nian Yaung , Yean-Kuen Fang
发明人： Tzu-Hsuan Hsu , Dun-Nian Yaung , Yean-Kuen Fang
IPC分类号： H01L21/00
CPC分类号： H01L27/14685 , H01L27/14621 , H01L27/14625
摘要： A device includes an image sensing element. The device also includes a Silicon Dioxide (SiO2) layer, located over the image sensing element, exhibiting a first index of refraction. The device further includes a first lens, located over the SiO2 layer, exhibiting a second index of refraction greater than the first index of refraction. The device still further includes a color filter located over the first lens and a second lens located over the color filter.
摘要翻译：一种装置包括图像感测元件。该装置还包括位于图像感测元件上方的呈现第一折射率的二氧化硅（SiO 2）层。该器件还包括位于SiO 2层之上的第一透镜，其具有大于第一折射率的第二折射率。该装置还包括位于第一透镜上方的滤色器和位于滤色器上方的第二透镜。

43. 发明授权

US07012240B2 Image sensor with guard rings and method for forming the same 有权
标题翻译：具有保护环的图像传感器及其形成方法
公开(公告)号：US07012240B2
公开(公告)日：2006-03-14
申请号：US10729406
申请日：2003-12-05
申请人： Dun-Nian Yaung
发明人： Dun-Nian Yaung
IPC分类号： H01J40/14 , H01L21/441
CPC分类号： H01L27/14625 , H01L27/14623 , H01L27/14643 , H01L27/14685 , H01L27/14687
摘要： An image sensor with air gaps as optical guard rings is provided. The air gaps are formed in a stacked insulating layer between the sensor areas, that is, around each pixel. A light transmitting insulating layer is formed on the stacked insulating layer without filling the air gaps.
摘要翻译：提供具有气隙作为光学保护环的图像传感器。气隙形成在传感器区域之间的堆叠绝缘层中，即围绕每个像素。在堆叠的绝缘层上形成透光绝缘层，而不填充气隙。

44. 发明授权

US06969899B2 Image sensor with light guides 有权
标题翻译：带导光板的图像传感器
公开(公告)号：US06969899B2
公开(公告)日：2005-11-29
申请号：US10728757
申请日：2003-12-08
申请人： Dun-Nian Yaung , Chung-Yi Yu
发明人： Dun-Nian Yaung , Chung-Yi Yu
IPC分类号： G02B6/00 , H01L21/00 , H01L27/146 , H01L31/00 , H01L31/0232
CPC分类号： H01L27/14685 , H01L27/1462 , H01L27/14623 , H01L27/14625
摘要： An image sensor device and fabrication method thereof. An image sensing array is formed in a substrate, wherein the image sensing array comprises a plurality of photosensors with spaces therebetween. A first dielectric layer with a first refractive index is formed overlying the spaces but not the photosensors. A conformal second dielectric layer with a second refractive index is formed on a sidewall of the first dielectric layer. A third dielectric layer with a third refractive index is formed overlying the photosensors but not the spaces. The third refractive index is greater than the second refractive index. A light guide constructed by the second and third dielectric layers is formed overlying each photosensor, thereby preventing incident light from striking other photosensors.
摘要翻译：一种图像传感器装置及其制造方法。图像感测阵列形成在基板中，其中图像感测阵列包括在其间具有间隔的多个光电传感器。具有第一折射率的第一介电层形成在空间上而不是光电传感器上。在第一介电层的侧壁上形成具有第二折射率的共形的第二介电层。形成具有第三折射率的第三介电层，覆盖光电传感器而不是空间。第三折射率大于第二折射率。由第二和第三电介质层构成的导光体形成在每个光电传感器上，从而防止入射光撞击其他感光体。

45. 发明申请

US20050179063A1 Image sensor with vertically integrated thin-film photodiode 失效
标题翻译：具有垂直集成薄膜光电二极管的图像传感器
公开(公告)号：US20050179063A1
公开(公告)日：2005-08-18
申请号：US10780790
申请日：2004-02-18
申请人： Dun-Nian Yaung , Sou-Kuo Wu , Ho-Ching Chien
发明人： Dun-Nian Yaung , Sou-Kuo Wu , Ho-Ching Chien
IPC分类号： H01L27/146 , H01L29/745 , H01L33/00 , H04N5/335
CPC分类号： H01L27/14636 , H01L27/14643
摘要： An image sensor with a vertically integrated thin-film photodiode includes a bottom doped layer of a PIN photodiode imbedded in a dielectric layer, wherein a bottom surface of the bottom doped layer completely contacts its corresponding underlying pixel electrode. The bottom doped layers of the PIN photodiodes are formed by a self-aligned and damascene method, therefore the pixel electrodes are not exposed to the I-type amorphous silicon layer of the PIN photodiodes. Moreover, the transparent electrode connects the PIN photodiodes to an external ground voltage power through a ground pad which is a portion of a top metal layer.
摘要翻译：具有垂直集成的薄膜光电二极管的图像传感器包括嵌入在电介质层中的PIN光电二极管的底部掺杂层，其中底部掺杂层的底表面完全接触其相应的底层像素电极。 PIN光电二极管的底部掺杂层通过自对准和镶嵌方法形成，因此像素电极不暴露于PIN光电二极管的I型非晶硅层。此外，透明电极通过作为顶部金属层的一部分的接地焊盘将PIN光电二极管连接到外部接地电压电力。

46. 发明授权

US06635936B1 SRAM layout for relaxing mechanical stress in shallow trench isolation technology 有权
标题翻译：在浅沟槽隔离技术中放松机械应力的SRAM布局
公开(公告)号：US06635936B1
公开(公告)日：2003-10-21
申请号：US09616975
申请日：2000-07-14
申请人： Shou-Gwo Wuu , Jin-Yuan Lee , Dun-Nian Yaung , Jeng-Han Lee
发明人： Shou-Gwo Wuu , Jin-Yuan Lee , Dun-Nian Yaung , Jeng-Han Lee
IPC分类号： H01L2976
CPC分类号： H01L27/1112 , Y10S257/903
摘要： An SRAM device has STI regions separated by mesas and doped regions including source/drain regions, active areas, wordline conductors and contacts in a semiconductor substrate is made with a source region has 90° transitions in critical locations. Form a dielectric layer above the active areas. Form the wordline conductors above the active areas transverse to the active areas. The source and drain regions of a pass gate transistor are on the opposite sides of a wordline conductor. Form the sidewalls along the crystal plane. Form the contacts extending down through to the dielectric layer to the mesas. Substrate stress is reduced because the large active area region formed in the substrate assures that the contacts are formed on the surfaces of the mesas are in contact with the mesas formed on the substrate and that the surfaces of the silicon of the mesas are shielded from the contacts.
摘要翻译： SRAM器件具有通过台面分隔的STI区域，并且包括源极/漏极区域，有源区域，字线导体和半导体衬底中的触点的掺杂区域由源区域在关键位置具有90°转变而制成。在有效区域之上形成介电层。在横向于有效区域的有效区域之上形成字线导体。栅极晶体管的源极和漏极区域位于字线导体的相对侧。沿着<100>晶面形成侧壁。形成触点向下延伸到电介质层到台面。衬底应力减小，因为形成在衬底中的大的有源区域区域确保在台面的<100>表面上形成的触点与形成在衬底上的台面接触，并且硅的<110>表面台面与触点屏蔽。

47. 发明授权

US06323054B1 Lateral P-I-N photodiode element with high quantum efficiency for a CMOS image sensor 有权
标题翻译：用于CMOS图像传感器的具有高量子效率的横向P-I-N光电二极管元件
公开(公告)号：US06323054B1
公开(公告)日：2001-11-27
申请号：US09583398
申请日：2000-05-31
申请人： Dun-Nian Yaung , Shou-Gwo Wuu , Chien-Hsien Tseng , Ching-Chun Wang
发明人： Dun-Nian Yaung , Shou-Gwo Wuu , Chien-Hsien Tseng , Ching-Chun Wang
IPC分类号： H01L2100
CPC分类号： H01L27/14609
摘要： A process for fabricating a lateral photodiode element, for an image sensor cell, with an increased depletion region, has been developed. The process features protecting a portion of the semiconductor substrate from ion implantation procedures used to create the P well, and the N well components of the lateral photodiode element. The protected region, or the space between the P well and N well regions, allows a larger depletion region to be realized, when compared to lateral photodiode elements in which the N well and P well regions butt. The space between the P well and N well regions, between about 0.2 to 0.4 um, result in the desired P well—intrinsic or P type semiconductor substrate—N well, (P-I-N), lateral photodiode element.
摘要翻译：已经开发了用于图像传感器单元的具有增加的耗尽区域的横向光电二极管元件的制造方法。该工艺特征是保护半导体衬底的一部分免受用于产生P阱的离子注入工艺和横向光电二极管元件的N阱部件。与N阱和P阱区对接的横向光电二极管元件相比，受保护区域或P阱和N阱区域之间的空间允许实现更大的耗尽区域。在P阱和N阱区之间的间隔在约0.2至0.4μm之间，导致所需的P本征或P型半导体衬底N阱（P-I-N），横向光电二极管元件。

48. 发明授权

US5998269A Technology for high performance buried contact and tungsten polycide gate integration 失效
标题翻译：技术用于高性能埋地接触和钨硅化合物门集成
公开(公告)号：US5998269A
公开(公告)日：1999-12-07
申请号：US35139
申请日：1998-03-05
申请人： Kuo-Ching Huang , Shou-Gwo Wuu , Jenn-Ming Huang , Dun-Nian Yaung
发明人： Kuo-Ching Huang , Shou-Gwo Wuu , Jenn-Ming Huang , Dun-Nian Yaung
IPC分类号： H01L21/285 , H01L21/336 , H01L21/768 , H01L21/8244 , H01L21/3215 , H01L21/335 , H01L21/74
CPC分类号： H01L27/11 , H01L21/28512 , H01L21/76895 , H01L29/66545
摘要： A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.
摘要翻译：描述了形成改进的埋地接触结的新方法。在半导体衬底的表面上设置栅极氧化硅层。沉积在栅极氧化物层上的多晶硅层。覆盖多晶硅层的硬掩模层被沉积。硬掩模和多晶硅层被蚀刻掉，其中它们不被掩模覆盖以形成多晶硅栅电极和互连线，其中间隙留在栅电极和互连线之间。介电材料层沉积在半导体衬底上以填补间隙。去除硬掩模层。多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。植入离子以形成埋入的接触。沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。去除介电材料层。沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

49. 发明授权

US5960276A Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process 有权
标题翻译：使用额外的硼注入来改善浅沟槽隔离工艺中的NMOS反向窄宽度效应
公开(公告)号：US5960276A
公开(公告)日：1999-09-28
申请号：US161406
申请日：1998-09-28
申请人： Jhon-Jhy Liaw , Dun-Nian Yaung , Jin-Yuan Lee
发明人： Jhon-Jhy Liaw , Dun-Nian Yaung , Jin-Yuan Lee
IPC分类号： H01L21/762 , H01L21/8238 , H01L21/76
CPC分类号： H01L21/76229 , H01L21/76232 , H01L21/76237 , H01L21/823878
摘要： A method to form, in a NMOS area, a shallow trench isolation (STI) having B doped sidewalls regions 44 to reduce the NMOS reverse narrow width effect in narrow active areas 12N (e.g., narrow channel regions
摘要翻译：在NMOS区域中形成具有B掺杂侧壁区域44的浅沟槽隔离（STI）以减小窄有源区12N（例如窄通道区域<0.1μm宽）中的NMOS反向窄宽度效应的方法。提供具有NMOS区域13和PMOS区域15的衬底。衬底氧化物层20和阻挡层22形成在衬底上。沟槽24在NMOS和PMOS区域中的衬底10中蚀刻。蚀刻形成窄的有源区域12N和宽的有源区域12W。狭窄的有源区域12N具有在0.4和1.0μm之间的宽度。在衬底上的沟槽的侧壁和底部上生长衬里层30。形成第一光致抗蚀剂层，覆盖PMOS区域并且在NMOS区域上具有第一开口。在关键步骤中，在衬底中形成硼掺杂区域44的沟槽的侧壁和底部中进行大角度硼注入。去除第一光致抗蚀剂层。绝缘层50形成在NMOS和PMOS区域的沟槽中。 PMOS区域中的PMOS场效应晶体管和NMOS区域中的NMOS场效应晶体管形成。本发明的硼掺杂区域44减小了NMOS区域中的反向窄的宽效应。

50. 发明授权

US09455288B2 Image sensor structure to reduce cross-talk and improve quantum efficiency 有权
标题翻译：图像传感器结构，减少串扰，提高量子效率
公开(公告)号：US09455288B2
公开(公告)日：2016-09-27
申请号：US13476785
申请日：2012-05-21
申请人： Shuang-Ji Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung , Jeng-Shyan Lin , Wen-De Wang
发明人： Shuang-Ji Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Feng-Chi Hung , Jeng-Shyan Lin , Wen-De Wang
IPC分类号： H01L31/0232 , H01L27/146
CPC分类号： H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/1464
摘要： A semiconductor device includes a substrate including a pixel region incorporating a photodiode, a grid disposed over the substrate and having walls defining a cavity vertically aligned with the pixel region, and a color filter material disposed in the cavity between the walls of the grid.
摘要翻译：半导体器件包括：衬底，其包括并入有光电二极管的像素区域，设置在衬底上的栅格，并且具有限定与像素区域垂直对准的空腔的壁;以及布置在栅格壁之间的空腔中的滤色器材料。

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