专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20050185441A1 Programmable MOS device formed by stressing polycrystalline silicon 失效
标题翻译：通过应力多晶硅形成的可编程MOS器件
公开(公告)号：US20050185441A1
公开(公告)日：2005-08-25
申请号：US10784705
申请日：2004-02-23
申请人： Chung-Hui Chen , Shun-Liang Hsu , Yean-Kuen Fang
发明人： Chung-Hui Chen , Shun-Liang Hsu , Yean-Kuen Fang
IPC分类号： G11C17/00 , G11C17/14
CPC分类号： G11C17/14
摘要： A programmable memory circuit and a method for programming the same are disclosed. A polycrystalline silicon resistor pair are used in a programmable memory cell. The pair includes a first polycrystalline silicon resistor stressable by a predetermined current thereacross, and a second polycrystalline silicon resistor similarly structured as the first polycrystalline silicon resistor stressable by the predetermined current, wherein when only the first resistor is stressed by the predetermined current, a resistance of the first resistor is lowered as compared to the unstressed second resistor, thereby programming the memory cell.
摘要翻译：公开了一种可编程存储器电路及其编程方法。在可编程存储器单元中使用多晶硅电阻器对。该对包括可以通过其中的预定电流强制的第一多晶硅电阻器和类似于由预定电流压力的第一多晶硅电阻器构成的第二多晶硅电阻器，其中当只有第一电阻器被预定电流施加时，电阻与未应力的第二电阻器相比降低第一电阻器，从而对存储器单元进行编程。

42. 发明申请

US20050055647A1 System and method for switching software functions 审中-公开
标题翻译：用于切换软件功能的系统和方法
公开(公告)号：US20050055647A1
公开(公告)日：2005-03-10
申请号：US10812873
申请日：2004-03-31
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： G06F3/048 , G09G5/00
CPC分类号： G06F3/0482 , G06F3/0489
摘要： A software function switching method and a system using the same that allows the user to set and operate a group of keys in an input unit as the hotkey sequence for switching and opening the sub-menu functions of application software. The user only needs to repeatedly press the first key of the hotkey sequence, and then intermittently press the second key of the hotkey sequence to send the input signals via the input unit into a data processing system. This method and system instructs the data processing system to count the number of times the user has pressed the hotkey, and, according to the count value, diagrams on the display unit corresponding to the sub-menu functions of the application software are sequentially switched and opened. When switched to the diagram for the sub-menu function that the user wishes to open, the first key of the hotkey is released, and the sub-menu function represented by the diagram can be opened. This allows the user to sequentially switch to and open every sub-menu function of the application software using only a set of hotkeys.
摘要翻译：一种软件功能切换方法及使用该软件功能切换方法的系统，其特征在于，允许用户将输入单元中的一组键设置和操作为用于切换和打开应用软件的子菜单功能的热键序列。用户只需要反复按热键序列的第一个键，然后间歇地按下热键序列的第二个键，通过输入单元将输入信号发送到数据处理系统中。该方法和系统指示数据处理系统对用户按下热键的次数进行计数，并且根据计数值，依次切换与应用软件的子菜单功能对应的显示单元上的图，开了当切换到用户希望打开的子菜单功能的图表时，热键的第一个键被释放，并且可以打开由图表示的子菜单功能。这允许用户仅使用一组热键顺序地切换并打开应用软件的每个子菜单功能。

43. 发明授权

US06638793B1 Methodology to pack standard staggered bond input-output buffer into linear input-output buffer 有权
标题翻译：将标准交错键输入输出缓冲器包装到线性输入输出缓冲器中的方法
公开(公告)号：US06638793B1
公开(公告)日：2003-10-28
申请号：US10086260
申请日：2002-03-04
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H01L2144
CPC分类号： H01L23/5286 , H01L23/50 , H01L24/06 , H01L2224/05554 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01075 , H01L2924/14 , H01L2924/00
摘要： A new method is provided that allows placing or stacking staggered bond I/O buffers into linear bond I/O buffers. The bond pads are linearly arranged, the interface between the staggered bond pad I/O buffers and the linearly arranged bond pads is achieved by a frame design that sequentially connects the staggered bond pad I/O buffers to the linearly arranged bond pads.
摘要翻译：提供了一种新的方法，允许将交错键I / O缓冲器放置或堆叠到线性键I / O缓冲器中。接合焊盘是线性布置的，交错键合焊盘I / O缓冲器和线性布置的接合焊盘之间的界面是通过将交错的焊盘I / O缓冲器顺序地连接到线性布置的接合焊盘的框架设计来实现的。

44. 发明授权

US06414534B1 Level shifter for ultra-deep submicron CMOS designs 有权
公开(公告)号：US06414534B1
公开(公告)日：2002-07-02
申请号：US09784819
申请日：2001-02-20
申请人： Wen-Tai Wang , Chung-Hui Chen
发明人： Wen-Tai Wang , Chung-Hui Chen
IPC分类号： H03L500
CPC分类号： H03K3/012 , H03K3/356113 , H03K3/356182
摘要： New level shifting circuits, one using dynamic current compensation and one using dynamic voltage equalization, are described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter input is connected to the input of the level shifting circuit to form an inverted level shifting input. A first NMOS transistor has the gate tied to the level shifting input and the source tied to ground. A first PMOS transistor has the gate tied to the level shifting output, the source tied to the high supply, and the drain tied to the first NMOS drain. A second NMOS transistor has the gate tied to the inverted level shifter input, the source tied to the ground, and the drain tied to the level shifting output. A second PMOS transistor has the gate tied to the first NMOS drain, the source tied to the high supply, and the drain is tied to the level shifting output. A third NMOS transistor has the gate tied to the first NMOS drain, v source tied to the level shifting input, and the drain tied to the level shifting output. A fourth NMOS transistor has the gate tied to the second NMOS drain, the source tied to the inverted level shifting input, and the drain tied to the first NMOS drain.

45. 发明授权

US06414524B1 Digital output buffer for MOSFET device 有权
标题翻译： MOSFET器件的数字输出缓冲器
公开(公告)号：US06414524B1
公开(公告)日：2002-07-02
申请号：US09812517
申请日：2001-03-20
申请人： Chung-Hui Chen
发明人： Chung-Hui Chen
IPC分类号： H03K300
CPC分类号： H03K17/164
摘要： A digital output buffer for an integrated circuit such as a MOSFET includes slew rate control and reduced crowbar current. The buffer includes pull-up and pull-down networks coupled between the input and output of the buffer. Each of the networks includes a plurality of conductive switch elements that are sequentially turned on or off by means of RC networks that control the switching delay between the conductive switch elements, and thus the slew rate of the buffer. The RC network includes a plurality of unbalanced passgates, each of which includes a high resistance and a low resistance that can be selectively coupled into circuit with the conductive switch elements so as to better control the timing of the turn on and turn off of the network, and thereby reduce crowbar currents.
摘要翻译：用于诸如MOSFET的集成电路的数字输出缓冲器包括压摆率控制和减少的消弧电流。缓冲器包括耦合在缓冲器的输入和输出之间的上拉和下拉网络。每个网络包括多个导电开关元件，其通过控制导电开关元件之间的开关延迟的RC网络依次导通或关断，从而缓冲器的转换速率。 RC网络包括多个不平衡传送门，每个不平衡传递门包括高电阻和低电阻，其可以选择性地与导电开关元件耦合到电路中，以便更好地控制网络的接通和断开的定时，从而减少撬棒电流。

46. 发明授权

US08878369B2 Low power/high speed TSV interface design 有权
标题翻译：低功耗/高速TSV接口设计
公开(公告)号：US08878369B2
公开(公告)日：2014-11-04
申请号：US13546024
申请日：2012-07-11
申请人： Chung-Hui Chen , Jaw-Juinn Horng , Shuo-Mao Chen , Der-Chyang Yeh
发明人： Chung-Hui Chen , Jaw-Juinn Horng , Shuo-Mao Chen , Der-Chyang Yeh
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L25/065 , H01L23/14 , H01L23/498
CPC分类号： H01L25/0657 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L2225/06572 , H01L2924/0002 , H01L2924/00
摘要： A TSV interface circuit for a TSV provided in an interposer substrate that forms a connection between a first die and a second die includes a driving circuit provided in the first die and a receiver circuit provided in the second die where the driving circuit is coupled to a first supply voltage and a second supply voltage that are both lower than the interposer substrate voltage that substantially reduces the parasitic capacitance of the TSV. The receiver circuit is also coupled to the first supply voltage and the second supply voltage that are both lower than the interposer substrate voltage.
摘要翻译：设置在形成第一管芯和第二管芯之间的连接的插入器基板中的TSV的TSV接口电路包括设置在第一管芯中的驱动电路和设置在第二管芯中的接收器电路，其中驱动电路耦合到第一电源电压和第二电源电压均低于基本上降低TSV的寄生电容的插入器基板电压。接收器电路还耦合到低于插入器基板电压的第一电源电压和第二电源电压。

47. 发明申请

US20130198710A1 SEMICONDUCTOR DEVICE FEATURE DENSITY GRADIENT VERIFICATION 有权
标题翻译：半导体器件特征密度梯度验证
公开(公告)号：US20130198710A1
公开(公告)日：2013-08-01
申请号：US13362914
申请日：2012-01-31
申请人： Young-Chow Peng , Chung-Hui Chen , Chien-Hung Chen , Po-Zeng Kang
发明人： Young-Chow Peng , Chung-Hui Chen , Chien-Hung Chen , Po-Zeng Kang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/70
摘要： A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.
摘要翻译：提供了一种用于验证半导体器件布局中存在可接受的器件特征梯度和器件特征差异的方法。该方法提供了将设备布局划分成多个窗口并且测量或以其他方式确定每个窗口内的设备特征密度。设备布局包括各种设备区域，并且该方法提供了将一个区域内的平均设备特征密度与周围区域或其他区域进行比较，并且还用于确定设备特征密度的梯度。可以从特定设备区域到周围区域监视梯度。用于执行该方法的指令可以存储在计算机可读存储介质上并由处理器执行。

48. 发明申请

US20130193499A1 DECOUPLING CAPACITOR AND LAYOUT FOR THE CAPACITOR 有权
标题翻译：解除电容器和电容器布局
公开(公告)号：US20130193499A1
公开(公告)日：2013-08-01
申请号：US13362411
申请日：2012-01-31
申请人： Chung-Hui CHEN
发明人： Chung-Hui CHEN
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L27/0629 , H01L27/0207 , H01L27/0811 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region.
摘要翻译：一种器件包括具有第一掺杂剂类型的第一和第二注入区的半导体衬底。栅极绝缘层和栅电极设置在第一和第二植入区域之间的电阻器区域的上方。第一介电层位于第一注入区上。提供一种接触结构，包括与门电极导电接触的第一接触部分，第一接触部分的至少一部分直接在栅电极上。第二接触部分直接接触第一接触部分并直接形成在第一介电层上。第三接触部分形成在第二植入区域上。

49. 发明申请

US20130185689A1 METHOD OF AND SYSTEM FOR GENERATING OPTIMIZED SEMICONDUCTOR COMPONENT LAYOUT 有权
标题翻译：用于生成优化的半导体元件布局的方法和系统
公开(公告)号：US20130185689A1
公开(公告)日：2013-07-18
申请号：US13352738
申请日：2012-01-18
申请人： Chien-Hung CHEN , Yung-Chow PENG , Chung-Hui CHEN , Chih Ming YANG
发明人： Chien-Hung CHEN , Yung-Chow PENG , Chung-Hui CHEN , Chih Ming YANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F2217/02 , G06F2217/06 , G06F2217/08 , G06F2217/12 , H01L27/0207 , H01L29/94
摘要： A method of generating an optimized layout of semiconductor components in conformance with a set of design rules includes generating, for a unit cell including one or more semiconductor components, a plurality of configurations each of which satisfies some, but not all, of the design rules. For each configuration, it is checked whether a layout, which is a repeating pattern of the unit cell, satisfies the remaining design rules. Among the configurations which satisfy all of the design rules, the configuration providing an optimal value of a property is selected for generating the optimized layout of the semiconductor components.
摘要翻译：根据一组设计规则生成半导体部件的优化布局的方法包括为包括一个或多个半导体部件的单元单元生成多个配置，每个配置满足设计规则的一些但不是全部。对于每个配置，检查作为单位单元的重复图案的布局是否满足剩余的设计规则。在满足所有设计规则的配置中，选择提供最佳的属性值的配置用于生成半导体部件的优化布局。

50. 发明申请

US20130175589A1 DECOUPLING CAPACITOR AND METHOD OF MAKING SAME 有权
公开(公告)号：US20130175589A1
公开(公告)日：2013-07-11
申请号：US13344137
申请日：2012-01-05
申请人： Chung-Hui CHEN
发明人： Chung-Hui CHEN
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/067 , H01L21/76224 , H01L23/5223 , H01L23/5286 , H01L27/0207 , H01L27/0629 , H01L27/0635 , H01L28/40 , H01L28/88 , H01L29/0649 , H01L29/66477 , H01L29/73 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式