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    • 41. 发明申请
    • Flexible mandril
    • 柔性木管
    • US20070135732A1
    • 2007-06-14
    • US11605019
    • 2006-11-28
    • Christopher DixonJames Carlson
    • Christopher DixonJames Carlson
    • A61B5/00
    • A61M25/09A61B2017/00292A61B2017/22038A61M2025/09083
    • A support member for providing core support to an elongated medical device. The support member comprises a generally cylindrical substrate having a proximal end and a distal end, and having a mass such that the respective proximal and distal ends are visible under medical imagery. The substrate is sized to be received in a lumen of the medical device, and has a plurality of grooves, axially disposed along the length of the substrate. The support member may have a greater number of grooves per unit length of the substrate at the distal end than at the proximal end, thereby imparting an increased flexibility to the distal end when compared to the proximal end.
    • 用于向细长的医疗装置提供芯支撑的支撑构件。 支撑构件包括具有近端和远端的大致圆柱形的基底,并且具有质量使得相应的近端和远端在医学图像下可见。 基板的尺寸被设计成容纳在医疗装置的内腔中,并且具有多个沿着基底的长度轴向设置的凹槽。 支撑构件可以在远端处的基底的每单位长度上具有比在近端处更多数量的凹槽,从而当与近端相比时,赋予远端更大的柔性。
    • 44. 发明授权
    • Multiple fan monitoring circuit for monitoring a number of fans utilizing a single sense input
    • 多风扇监控电路,用于利用单个感测输入来监视多个风扇
    • US06757617B2
    • 2004-06-29
    • US09768074
    • 2001-01-23
    • Robert Christopher DixonChad J. Larson
    • Robert Christopher DixonChad J. Larson
    • G05D2300
    • H05K7/20836G06F1/206
    • A multiple fan monitoring circuit for use with a plurality of fans, wherein each of the fans operates at a different frequency and generates a tach signal indicative of the fan operation, including a number of waveform shaping networks coupled to a corresponding one of the fans and utilized to waveshape a tach signal generated by its corresponding fan. The multiple fan monitoring circuit also includes a frequency processing circuit, coupled to the waveform shaping networks, that receives the waveshaped tach signals at a single sense node. The frequency processing circuit includes a summing circuit, coupled to the single sense node, that combines the waveshaped tach signals into a single combined signal, and a frequency discriminator, coupled to the summing circuit, that separates the single combined signal into multiple components, wherein each of the multiple components corresponds to a particular fan.
    • 一种与多个风扇一起使用的多风扇监测电路,其中每个风扇以不同的频率工作,并产生指示风扇运行的信号,包括耦合到相应的一个风扇的多个波形整形网络,以及 用于对其相应风扇产生的信号进行波形拍摄。 多风扇监测电路还包括耦合到波形整形网络的频率处理电路,其在单个感测节点处接收波形tach信号。 频率处理电路包括耦合到单个感测节点的将波形tach信号组合成单个组合信号的求和电路,以及耦合到求和电路的将单个组合信号分离成多个分量的频率鉴别器,其中 多个组件中的每一个对应于特定的风扇。
    • 45. 发明授权
    • Method and apparatus for error injection techniques
    • 误差注入技术的方法和装置
    • US5875195A
    • 1999-02-23
    • US829087
    • 1997-03-31
    • Robert Christopher Dixon
    • Robert Christopher Dixon
    • G06F12/16G06F11/22G06F11/26G06F11/00
    • G06F11/2284G06F11/261
    • A process and implementing computer system in which a power-on self-test (POST) routine initially clears 203 a mask register 111 which is effective to mask or block data from being written to addresses in a synchronous DRAM or SDRAM 107. After disabling interrupts and caches, the tested SDRAM memory 107 is cleared to all "0"s. Sequential data byte lanes are tested by writing bits in a predetermined pattern to inject errors at predetermined bytes in SDRAM, setting selected mask register bits and then writing all "0"s to the predetermined addresses. The tested memory locations are read and compared with the predetermined pattern for errors. Detected errors are noted by recordation and the memory locations are cleared as the method recycles until all of the data byte lanes have been tested and the results recorded.
    • 其中上电自检(POST)程序最初清除203个屏蔽寄存器111的过程和实现计算机系统,其有效地屏蔽或阻止数据被写入同步DRAM或SDRAM 107中的地址。在禁用中断之后 和高速缓存,被测试的SDRAM存储器107被清除为全部“0”。 通过以预定模式写入位来测试顺序数据字节通道,以在SDRAM中的预定字节处注入错误,设置所选择的掩码寄存器位,然后将所有“0”写入预定地址。 读取测试的存储器位置并将其与用于错误的预定模式进行比较。 通过记录记录检测到的错误,并且随着方法的回收,清除存储器位置,直到所有的数据字节通道都被测试并且记录结果。
    • 46. 发明授权
    • ECC memory multi-bit error generator
    • ECC存储器多位错误发生器
    • US5872790A
    • 1999-02-16
    • US808411
    • 1997-02-28
    • Robert Christopher Dixon
    • Robert Christopher Dixon
    • G06F11/10H03M13/01G06F11/00
    • G06F11/10H03M13/01
    • An error generator for use with a memory device, such as dynamic random-access memory (DRAM) which is connected to an error detection or correction device, such as a memory controller using error-correcting code. The memory error generator uses a clock signal provided by the computer system, determines when the computer system first attempts to read from a data stream after synchronization, and thereafter introduces the error in at least one bit of the data stream by complementing the bit. The error generator can be provided with a switch such that synchronization is performed in response to activation of the switch. The error generator preferably is constructed using an inexpensive device, such as a programmable array logic (PAL) circuit. Use of a PAL allows the bit complementing to occur quickly enough to meet timing requirements of the memory controller. The PAL and switch can be mounted on an interposer which is removably connected to the memory array and the memory controller.
    • 与存储器件一起使用的错误发生器,例如连接到错误检测或校正装置的动态随机存取存储器(DRAM),诸如使用纠错码的存储器控​​制器。 存储器错误发生器使用由计算机系统提供的时钟信号,确定计算机系统何时首先尝试在同步之后从数据流读取,然后通过补充该位来在该数据流的至少一位中引入该错误。 错误发生器可以设置有开关,使得响应于开关的激活而执行同步。 误差发生器优选地使用诸如可编程阵列逻辑(PAL)电路的廉价器件来构造。 使用PAL允许位补码发生得足够快以满足存储器控制器的时序要求。 PAL和开关可以安装在可拆卸地连接到存储器阵列和存储器控制器的插入器上。