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41. 发明申请

US20130086586A1 Issuing Requests To A Fabric 有权
公开(公告)号：US20130086586A1
公开(公告)日：2013-04-04
申请号：US13248276
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
IPC分类号： G06F9/46
CPC分类号： G06F13/4221 , G06F13/366 , G06F13/368 , G06F13/4022 , G06F15/7807 , G06F15/7864
摘要： In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.

42. 发明授权

US07536473B2 General input/output architecture, protocol and related methods to implement flow control 有权
标题翻译：一般输入/输出架构，协议和相关方法来实现流量控制
公开(公告)号：US07536473B2
公开(公告)日：2009-05-19
申请号：US10227601
申请日：2002-08-23
申请人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
发明人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
IPC分类号： G06F15/16
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output communication architecture, protocol and related methods are presented.
摘要翻译：提出了一种增强的通用输入/输出通信架构，协议和相关方法。

43. 发明申请

US20080162962A1 TERMINATION TECHNIQUES FOR BUS INTERFACES 有权
标题翻译：总线接口终接技术
公开(公告)号：US20080162962A1
公开(公告)日：2008-07-03
申请号：US11618496
申请日：2006-12-29
申请人： Blaise Fanning
发明人： Blaise Fanning
IPC分类号： G06F1/26
CPC分类号： G06F1/3253 , G06F1/3228 , Y02D10/151 , Y02D50/20
摘要： Techniques involving the transfer of signals across interconnection media are disclosed. For instance, an apparatus may include an apparatus having an interconnection medium, a first device that may drive the interconnection medium, and a second device. The second device may include a pull-up resistor that is selectively coupled between the interconnection medium and a power source. For instance, the second device may disconnect a power source from the interconnection medium when the first device is in a power saving operational state. Otherwise, the pull-up resistance is coupled between the power source and the interconnection medium.
摘要翻译：公开了涉及通过互连介质传送信号的技术。例如，设备可以包括具有互连介质的设备，可以驱动互连介质的第一设备和第二设备。第二装置可以包括上拉电阻器，其被选择性地耦合在互连介质和电源之间。例如，当第一设备处于节电操作状态时，第二设备可以断开电源与互连介质的连接。否则，上拉电阻耦合在电源和互连介质之间。

44. 发明申请

US20080077720A1 Isochronous memory access with variable channel priorities and timers 审中-公开
标题翻译：具有可变通道优先级和定时器的同步存储器访问
公开(公告)号：US20080077720A1
公开(公告)日：2008-03-27
申请号：US11528025
申请日：2006-09-27
申请人： Blaise Fanning
发明人： Blaise Fanning
IPC分类号： G06F13/14
CPC分类号： G06F13/1642
摘要： A memory controller to arbitrate memory request queues based upon priorities corresponding to the request queues, comprising logic to serve the request queue whose priority is equal to the maximum of the priorities. An embodiment may further comprise a timer corresponding to a request queue, where the priority of the request queue is changed from a low value to a high value if the timer expires while the request queue is not empty. In some embodiments, when the request queue is emptied after its timer has expired, the timer is set, and then started again once a new request enters the empty request queue.
摘要翻译：一种存储器控制器，用于基于对应于所述请求队列的优先级来仲裁存储器请求队列，包括用于服务优先级等于所述优先级的最大值的所述请求队列的逻辑。实施例还可以包括对应于请求队列的定时器，其中如果定时器在请求队列不为空时到期，则请求队列的优先级从低值改变为高值。在一些实施例中，当请求队列在其定时器到期之后被清空时，定时器被置位，然后一旦新的请求进入空的请求队列就再次启动。

45. 发明申请

US20070038793A1 General input/output architecture, protocol and related methods to manage data integrity 有权
标题翻译：一般输入/输出架构，协议和相关方法来管理数据完整性
公开(公告)号：US20070038793A1
公开(公告)日：2007-02-15
申请号：US11585648
申请日：2006-10-23
申请人： Eric Wehage , Jasmin Ajanovic , David Harriman , David Lee , Blaise Fanning , Buck Gremel , Ken Creta , Wayne Moore
发明人： Eric Wehage , Jasmin Ajanovic , David Harriman , David Lee , Blaise Fanning , Buck Gremel , Ken Creta , Wayne Moore
IPC分类号： G06F13/14
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output communication architecture, protocol and related methods are presented.
摘要翻译：提出了一种增强的通用输入/输出通信架构，协议和相关方法。

46. 发明申请

US20050144393A1 Dedicated cache memory 有权
标题翻译：专用高速缓存
公开(公告)号：US20050144393A1
公开(公告)日：2005-06-30
申请号：US10750148
申请日：2003-12-31
申请人： Blaise Fanning
发明人： Blaise Fanning
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0842
摘要： A method and apparatus for a dedicated cache memory are described. Under an embodiment of the invention, a cache memory includes a general-purpose sector and a dedicated sector. The general-purpose sector is to be used for general computer operations. The dedicated sector is to be dedicated to use for a first computer process.
摘要翻译：描述专用高速缓冲存储器的方法和装置。在本发明的一个实施例中，高速缓存存储器包括通用扇区和专用扇区。通用部门将用于通用计算机操作。专门的部门将专门用于第一个计算机进程。

47. 发明申请

US20050138251A1 Arbitration of asynchronous and isochronous requests 审中-公开
标题翻译：异步和等时请求的仲裁
公开(公告)号：US20050138251A1
公开(公告)日：2005-06-23
申请号：US10740738
申请日：2003-12-18
申请人： Blaise Fanning
发明人： Blaise Fanning
IPC分类号： G06F13/00 , G06F13/16
CPC分类号： G06F13/161
摘要： Machine-readable media, methods, and apparatus are described to arbitrate between asynchronous requests and isochronous requests. In one embodiment, an arbiter defines a service period comprising an asynchronous portion followed by an isochronous portion. During the asynchronous portion, the arbiter first services asynchronous requests and then services isochronous requests if no asynchronous requests are available. In response to servicing an isochronous request during the asynchronous portion, the arbiter lengthens the asynchronous portion and shortens the isochronous portion for the current service period. During the isochronous portion, the arbiter services isochronous requests and does not service asynchronous requests.
摘要翻译：描述了机器可读介质，方法和装置以在异步请求和等时请求之间进行仲裁。在一个实施例中，仲裁器定义包括异步部分的后续的同步部分的服务周期。在异步部分期间，仲裁器首先服务异步请求，然后在没有异步请求可用的情况下服务同步请求。响应于在异步部分期间服务等时请求，仲裁器延长异步部分并缩短当前服务周期的同步部分。在同步部分期间，仲裁器服务同步请求并且不服务异步请求。

48. 发明授权

US09652259B2 Apparatus and method for managing register information in a processing system 有权
公开(公告)号：US09652259B2
公开(公告)日：2017-05-16
申请号：US14008196
申请日：2011-10-01
申请人： Blaise Fanning , Anil K. Sabbavarapu
发明人： Blaise Fanning , Anil K. Sabbavarapu
IPC分类号： G06F9/445 , G06F11/14
CPC分类号： G06F9/44505 , G06F11/1441 , Y02D10/43
摘要： The setting in a configuration register is controlled based on a value stored in a management register and/or based on generation of a reset signal during a debugging operation or detection of a malfunction or power state transition in an electronic system. The management register may allocate a single bit to each configuration register, and the setting to be loaded into the configuration register is to be controlled based on the value of the bit. Additionally, or alternatively, the setting in the configuration register may be controlled when the reset signal assumes a value indicating that a default setting is to be stored.

49. 发明申请

US20160034345A1 MEMORY LATENCY MANAGEMENT 有权
标题翻译：内存管理
公开(公告)号：US20160034345A1
公开(公告)日：2016-02-04
申请号：US14775848
申请日：2014-02-26
申请人： Robert J. ROYER, JR. , Blaise FANNING , Eng Hun OOI , INTEL CORPORATION
发明人： Robert J. Royer, Jr. , Blaise Fanning , Eng Hun Ooi
IPC分类号： G06F11/10 , G06F12/08
CPC分类号： G06F11/1064 , G06F11/1048 , G06F12/084 , G06F12/0866 , G06F2212/1032 , G06F2212/313
摘要： Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.
摘要翻译：描述了用于管理存储器延迟操作的装置，系统和方法。在一个实施例中，电子设备包括处理器和用于从远程存储器设备接收数据的存储器控制逻辑，将数据存储在本地高速缓冲存储器中，接收与数据相关联的纠错码指示符，以及实现数据管理策略响应于纠错码指示器。还公开并要求保护其他实施例。

50. 发明授权

US09195589B2 Adaptive configuration of non-volatile memory 有权
标题翻译：非易失性存储器的自适应配置
公开(公告)号：US09195589B2
公开(公告)日：2015-11-24
申请号：US13977084
申请日：2011-12-27
申请人： Shekoufeh Qawami , Rajesh Sundaram , David J. Zimmerman , Blaise Fanning
发明人： Shekoufeh Qawami , Rajesh Sundaram , David J. Zimmerman , Blaise Fanning
IPC分类号： G06F3/00 , G06F12/02 , G06F9/30 , G06F1/32 , G11C16/06
CPC分类号： G11C13/0038 , G06F1/3275 , G06F9/30101 , G06F12/0246 , G11C13/0004 , G11C13/0033 , G11C16/06 , Y02D10/14
摘要： Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.
摘要翻译：公开了用于非易失性存储器的自适应配置的示例。示例包括配置为包括默认值和更新值以指示非易失性存储器的一个或多个配置的模式寄存器。这些示例还可以包括可以指示存储器地址长度和/或操作功率状态的配置表中维护的可发现功能。

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