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41. 发明申请

US20080136462A1 Apparatus and method of generating DBI signal in semiconductor integrated circuit 有权
标题翻译：在半导体集成电路中产生DBI信号的装置和方法
公开(公告)号：US20080136462A1
公开(公告)日：2008-06-12
申请号：US11878091
申请日：2007-07-20
申请人： Beom Ju Shin
发明人： Beom Ju Shin
IPC分类号： H03K5/00
CPC分类号： H03K19/0016
摘要： An apparatus for generating a DBI signal in a semiconductor integrated circuit includes a full adder that includes data input terminals and a carry input terminal, each of which receives data, performs an operation on the received data, thereby outputting a sum and a carry. A half adder includes data input terminals, each of which receives data, performs an operation on the received data, thereby outputting a sum and a carry. A DBI determining unit determines a logic value of each of the data according to the sums and the carries that are transmitted from the full adder and the half adder, thereby outputting a DBI signal.
摘要翻译：一种用于在半导体集成电路中产生DBI信号的装置包括：全加器，包括数据输入端和进位输入端，每个输入端接收数据，对所接收的数据进行操作，从而输出和和进位。半加法器包括数据输入端，每个数据输入端接收数据，对接收到的数据执行操作，从而输出和和进位。 DBI确定单元根据从全加器和半加法器发送的总和和运算来确定每个数据的逻辑值，从而输出DBI信号。

42. 发明申请

US20070069782A1 Delay locked loop for high speed semiconductor memory device 有权
标题翻译：延迟锁定环路用于高速半导体存储器件
公开(公告)号：US20070069782A1
公开(公告)日：2007-03-29
申请号：US11528633
申请日：2006-09-28
申请人： Beom-Ju Shin
发明人： Beom-Ju Shin
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A delayed locked loop supports increased operation frequency in a semiconductor memory device. An output driver for use in a delay locked loop includes a first driving block for receiving an output from the delay locked loop to generate a first DLL clock for outputting read data corresponding to a read command, and a second driving block for receiving an output from the delay locked loop to generate a second DLL clock for reducing current consumption during a write operation, wherein the first driving block has larger delay amount than the second driving block.
摘要翻译：延迟锁定环路支持半导体存储器件中增加的操作频率。用于延迟锁定环路的输出驱动器包括用于接收来自延迟锁定环路的输出的第一驱动块，以产生用于输出与读取命令对应的读取数据的第一DLL时钟，以及用于接收来自所述延迟锁定环路产生用于在写入操作期间减少电流消耗的第二DLL时钟，其中所述第一驱动块具有比所述第二驱动块更大的延迟量。

43. 发明授权

US07046575B2 Bus connection circuit for read operation of multi-port memory device 有权
标题翻译：总线连接电路，用于多端口存储器件的读取操作
公开(公告)号：US07046575B2
公开(公告)日：2006-05-16
申请号：US10876504
申请日：2004-06-24
申请人： Beom-Ju Shin
发明人： Beom-Ju Shin
IPC分类号： G11C8/00
CPC分类号： G11C5/063 , G11C7/065 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1075 , G11C8/16 , G11C11/4091 , G11C11/4096 , G11C2207/002
摘要： There is provided a semiconductor memory design technique, specifically a bus connection circuit for a read operation of a multi-port memory device. The bus connection circuit is adapted to a current sensing type bus transmission/reception structure. The bus connection circuit includes: a read data sensing/latching unit for sensing/latching a read data applied on a local data bus in response to a read data strobe signal; and a read data driving unit for driving the data latched in the read data sensing/latching unit to a global data bus in response to a read data driving pulse, and for connecting or disconnecting a path of current flowing the global data bus according to a logic level of the latched data.
摘要翻译：提供了半导体存储器设计技术，特别是用于多端口存储器件的读取操作的总线连接电路。总线连接电路适用于电流感测型总线发送/接收结构。总线连接电路包括：读取数据感测/锁存单元，用于响应于读取的数据选通信号来感测/锁存施加在本地数据总线上的读取数据; 以及读取数据驱动单元，用于响应于读取的数据驱动脉冲将锁存在读取数据感测/锁存单元中的数据驱动到全局数据总线，并且根据读取数据驱动脉冲连接或断开流动全局数据总线的电流的路径锁存数据的逻辑电平。

44. 发明授权

US06996027B2 Synchronous memory device 有权
标题翻译：同步存储设备
公开(公告)号：US06996027B2
公开(公告)日：2006-02-07
申请号：US10876412
申请日：2004-06-25
申请人： Beom-Ju Shin
发明人： Beom-Ju Shin
IPC分类号： G11C8/00
CPC分类号： G11C7/1075 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087
摘要： A synchronous memory device and a synchronous multi-port memory device preventing a skew between data and data strobe signal according to data transmission path is disclosed. In order to eliminate such a position dependence, the synchronous memory device and the synchronous multi-port memory device adopt a scheme of transmitting the data strobe signal together with the data. If a data driving block transmits the data capture pulse together with the data, the data and the data capture pulse pass the same delay without regard to the data transmission/reception blocks, thus preventing the occurrence of the skew. In other words, the present invention adopts a source synchronization scheme, which is used at an outside of the conventional synchronous DRAM, into the memory device. Specifically, the present invention can be applied to a synchronous multi-port memory device having a plurality of independent ports.
摘要翻译：公开了一种根据数据传输路径防止数据和数据选通信号之间的偏斜的同步存储器件和同步多端口存储器件。为了消除这样的位置依赖性，同步存储器件和同步多端口存储器件采用与数据一起发送数据选通信号的方案。如果数据驱动块与数据一起发送数据捕获脉冲，则数据和数据捕获脉冲通过相同的延迟而不考虑数据发送/接收块，从而防止发生偏斜。换句话说，本发明采用在传统的同步DRAM的外部使用的源同步方案到存储器件中。具体地，本发明可以应用于具有多个独立端口的同步多端口存储器件。

45. 发明授权

US08483005B2 Internal signal generator for use in semiconductor memory device 有权
标题翻译：用于半导体存储器件的内部信号发生器
公开(公告)号：US08483005B2
公开(公告)日：2013-07-09
申请号：US11477540
申请日：2006-06-30
申请人： Beom-Ju Shin
发明人： Beom-Ju Shin
IPC分类号： G11C8/18 , G11C8/04
CPC分类号： G11C19/00 , G11C7/1039 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C11/4076 , G11C11/4082
摘要： A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches, each of which latches an external address in response to the activation of an external command and outputs an internal address in response to the activation of an internal command corresponding to the external command. A pipe latch control unit is configured to control the pipe latch unit to sequentially enable the plurality of pipe latches. An output drive unit is configured to selectively output the internal address or the external address. The internal command is activated after a predetermined latency from an activation timing of the external command.
摘要翻译：半导体存储器件包括具有多个管道锁存器的管道锁存单元，每个管道锁存器响应于外部命令的激活而锁存外部地址，并且响应于对应于外部命令的内部命令的激活而输出内部地址命令。管闩锁控制单元被配置为控制管闩锁单元以顺序启用多个管闩。输出驱动单元被配置为选择性地输出内部地址或外部地址。在从外部命令的激活定时开始的预定延迟之后，内部命令被激活。

46. 发明授权

US08437203B2 Nonvolatile memory apparatus and method for processing configuration information thereof 有权
标题翻译：非易失性存储装置及其配置信息的处理方法
公开(公告)号：US08437203B2
公开(公告)日：2013-05-07
申请号：US12983138
申请日：2010-12-31
申请人： Kyoung Nam Kim , Beom Ju Shin
发明人： Kyoung Nam Kim , Beom Ju Shin
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C16/20
摘要： A nonvolatile memory apparatus includes a memory device having a configuration information storage block for storing a first configuration data group and a second configuration data group having fewer bits than the first configuration data group and a configuration information processing circuit configured to determine a majority of the first configuration data group outputted from the memory device, during a first period of a power-up operation, and determine a majority of the second configuration data group outputted from the memory device, during a second period after the first period.
摘要翻译：非易失性存储装置包括存储装置，具有用于存储第一配置数据组的配置信息存储块和比第一配置数据组少的位的第二配置数据组，配置信息处理电路被配置为确定第一配置数据组的大部分配置数据组在上电操作的第一周期期间从存储器件输出，并且在第一周期之后的第二周期期间确定从存储器件输出的大部分第二配置数据组。

47. 发明授权

US08347198B2 Semiconductor memory device having capability of stable initial operation 有权
公开(公告)号：US08347198B2
公开(公告)日：2013-01-01
申请号：US12217064
申请日：2008-06-30
申请人： Beom-Ju Shin , Sang-Sic Yoon
发明人： Beom-Ju Shin , Sang-Sic Yoon
IPC分类号： G06F11/08 , G06F11/30
CPC分类号： G06F11/1004
摘要： A semiconductor memory device is capable of outputting a preset logic level through an EDC pin according to an operation mode during an initial operation, and providing a stable operation according to the specification of the semiconductor memory device just after the input of a data clock (WCK). The semiconductor memory device includes an output circuit configured to output a synchronous data in response to a data clock when the data clock is enabled, and output an asynchronous data when the data clock is disabled, and a data clock detection circuit configured to control outputting the asynchronous data by checking whether the data clock is in a stable state or not.

48. 发明授权

US08284602B2 Pipe latch circuit of multi-bit prefetch-type semiconductor memory device with improved structure 有权
标题翻译：具有改进结构的多位预取型半导体存储器件的管锁存电路
公开(公告)号：US08284602B2
公开(公告)日：2012-10-09
申请号：US13216799
申请日：2011-08-24
申请人： Beom Ju Shin
发明人： Beom Ju Shin
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/103 , G11C7/1039 , G11C7/106
摘要： Provided is a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device with an advanced structure. The pipe latch circuit of the present invention comprises: a first latch circuit for latching pre-fetched plural bits of input data from global input/output lines; a first multiplexing circuit comprises a first multiplexer for selecting a certain input data from first group of the input data in response to a first selection control signal and a second multiplexer for selecting a certain input data from second group of the input data in response to a second selection control signal; a second multiplexing circuit for setting a sequence of output data from the first multiplexing circuit in response to a third selection control signal; and a second latch circuit comprises a third latch for latching a first output data from the second multiplexing circuit in response to a first output latch control signal and a fourth latch for latching a second output data from the second multiplexing circuit in response to a second output latch control signal. The invention cuts down the overall chip size and current consumption of the pipe latch circuit by reducing the number of multiplexers necessary for arranging the pre-fetched data in a predetermined output order.
摘要翻译：提供具有先进结构的多位预取型半导体存储器件的管锁存电路。本发明的管锁电路包括：第一锁存电路，用于锁存来自全局输入/输出线的预取多位输入数据; 第一多路复用电路包括第一多路复用器，用于响应于第一选择控制信号从第一组输入数据中选择特定输入数据，以及第二多路复用器，用于响应于第一多路复用器从第二组输入数据中选择某一输入数据第二选择控制信号; 第二复用电路，用于响应于第三选择控制信号设置来自第一多路复用电路的输出数据序列; 并且第二锁存电路包括第三锁存器，用于响应于第一输出锁存控制信号锁存来自第二复用电路的第一输出数据;以及第四锁存器，用于响应于第二输出锁存来自第二复用电路的第二输出数据锁存控制信号。本发明通过减少以预定的输出顺序排列预取的数据所需的多路复用器的数量来减少管锁存电路的整体芯片尺寸和电流消耗。

49. 发明授权

US08154948B2 Method of operating nonvolatile memory device 有权
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US08154948B2
公开(公告)日：2012-04-10
申请号：US12701877
申请日：2010-02-08
申请人： Beom Ju Shin
发明人： Beom Ju Shin
IPC分类号： G11C8/00
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/26
摘要： A method of operating a nonvolatile memory device includes supplying a variable voltage of a first voltage level to a selected page buffer and supplying the variable voltage to a first bit line, coupled to a selected memory cell selected for data reading, for a first time period, cutting off the supply of the variable voltage to the first bit line, after the first time period, and precharging the first bit line to a second voltage level through a sense node of the selected page buffer, which is in a precharge state, evaluating a voltage of the first bit line, after the precharging of the first bit line, so that the voltage of the first bit line is shifted according to a program state of the selected memory cell, and sensing the voltage of the evaluated first bit line and latching data in the selected memory cell.
摘要翻译：一种操作非易失性存储器件的方法包括：将第一电压电平的可变电压提供给所选择的页面缓冲器，并将可变电压提供给第一位线，该第一位线耦合到第一时间段中被选择用于数据读取的所选存储器单元在第一时间段之后切断对第一位线的可变电压的供应，并且通过处于预充电状态的所选择的页面缓冲器的感测节点将第一位线预充电到第二电压电平，评估第一位线的电压在第一位线的预充电之后，使得第一位线的电压根据所选存储单元的编程状态而偏移，并且感测所评估的第一位线的电压，以及在所选存储单元中锁存数据。

50. 发明申请

US20120032706A1 MULTI-CHIP PACKAGE 有权
标题翻译：多芯片包装
公开(公告)号：US20120032706A1
公开(公告)日：2012-02-09
申请号：US12982544
申请日：2010-12-30
申请人： Kyoung Nam KIM , Beom Ju Shin
发明人： Kyoung Nam KIM , Beom Ju Shin
IPC分类号： H03K3/00
CPC分类号： H03K19/00346
摘要： A multi-chip package includes a plurality of chips coupled in parallel to an I/O pad and an output driver circuit included in each of the chips and configured to transmit output data to the I/O pad. The driving force of the output driver circuit is controlled on the basis of stack information indicative of the number of chips being activated.
摘要翻译：多芯片封装包括与I / O焊盘并联耦合的多个芯片和包括在每个芯片中的输出驱动器电路，并被配置为将输出数据发送到I / O焊盘。输出驱动电路的驱动力是根据表示正在激活的芯片数量的堆栈信息进行控制的。

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