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41. 发明申请

US20180012829A1 SEMICONDUCTOR PACKAGE WITH CLIP ALIGNMENT NOTCH 有权
公开(公告)号：US20180012829A1
公开(公告)日：2018-01-11
申请号：US15207462
申请日：2016-07-11
申请人： Amkor Technology, Inc.
发明人： Marc Alan Mangrum
IPC分类号： H01L23/495 , H01L23/00
CPC分类号： H01L23/49575 , H01L23/49513 , H01L23/49517 , H01L23/49524 , H01L23/49548 , H01L23/49562 , H01L23/49565 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/69 , H01L24/73 , H01L24/83 , H01L24/84 , H01L24/92 , H01L2224/29101 , H01L2224/32145 , H01L2224/32245 , H01L2224/37012 , H01L2224/37147 , H01L2224/40245 , H01L2224/48247 , H01L2224/69 , H01L2224/73263 , H01L2224/73265 , H01L2224/83801 , H01L2224/84205 , H01L2224/84214 , H01L2224/84385 , H01L2224/84801 , H01L2224/8484 , H01L2224/8485 , H01L2224/84986 , H01L2224/92246 , H01L2924/00014 , H01L2924/1306 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2924/014 , H01L2924/00
摘要： An electronic component includes a leadframe and a first semiconductor die. The leadframe includes a leadframe top side, a leadframe bottom side opposite the leadframe top side, and a top notch at the leadframe top side. The top notch includes a top notch base located between the leadframe top side and the leadframe bottom side, and defining a notch length of the top notch, and can also include a top notch first sidewall extended, along the notch length, from the leadframe top side to the top notch base. The first semiconductor die can include a die top side a die bottom side opposite the die top side and mounted onto the leadframe top side, and a die perimeter. The top notch can be located outside the die perimeter. Other examples and related methods are also disclosed herein.

42. 发明授权

US09831282B2 Electronic device package and fabricating method thereof 有权
公开(公告)号：US09831282B2
公开(公告)日：2017-11-28
申请号：US15248687
申请日：2016-08-26
申请人： Amkor Technology, Inc.
发明人： Jin Young Kim , No Sun Park , Yoon Joo Kim , Seung Jae Lee , Se Woong Cha , Sung Kyu Kim , Ju Hoon Yoon
IPC分类号： H01L29/06 , H01L27/146 , H01L23/00 , H01L23/498 , H01L23/528 , G06K9/00
CPC分类号： H01L27/14636 , G06K9/00006 , H01L21/568 , H01L23/49811 , H01L23/49827 , H01L23/5286 , H01L24/19 , H01L24/20 , H01L27/14618 , H01L27/14678 , H01L2224/04105 , H01L2224/211 , H01L2224/214 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2924/00
摘要： Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 μm or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof.

43. 发明授权

US09673122B2 Micro lead frame structure having reinforcing portions and method 有权
公开(公告)号：US09673122B2
公开(公告)日：2017-06-06
申请号：US14839956
申请日：2015-08-29
申请人： AMKOR TECHNOLOGY, INC.
发明人： Hyeong Il Jeon , Hyung Kook Chung , Hong Bae Kim , Byong Jin Kim
IPC分类号： H01L23/495 , H01L23/31 , H01L23/00
CPC分类号： H01L23/3114 , H01L23/3107 , H01L23/49541 , H01L23/49548 , H01L24/97 , H01L2224/48091 , H01L2224/48247 , H01L2224/97 , H01L2924/00014
摘要： In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes.

44. 发明授权

US09653428B1 Semiconductor package and fabricating method thereof 有权
公开(公告)号：US09653428B1
公开(公告)日：2017-05-16
申请号：US15207186
申请日：2016-07-11
申请人： Amkor Technology, Inc.
发明人： David Hiner , Michael Kelly , Ronald Huemoeller
IPC分类号： H01L23/48 , H01L23/52 , H01L25/065 , H01L25/00 , H01L23/538 , H01L23/00 , H01L21/56
CPC分类号： H01L25/0655 , H01L21/563 , H01L23/5383 , H01L23/5386 , H01L24/14 , H01L24/16 , H01L24/73 , H01L24/97 , H01L25/50 , H01L2224/1403 , H01L2224/16225 , H01L2224/73204 , H01L2224/95001 , H01L2224/97
摘要： A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die.

45. 发明授权

US09633932B2 Lead frame package having discharge hole and method of manufacturing the same 有权
公开(公告)号：US09633932B2
公开(公告)日：2017-04-25
申请号：US14722110
申请日：2015-05-26
申请人： AMKOR TECHNOLOGY, INC.
发明人： Kyoung Yeon Lee , Byong Jin Kim , Kyung Su Kim , Hyung Il Jeon , Jae Doo Kwon
IPC分类号： H01L23/495 , H01L23/043 , H01L23/31 , H01L21/50 , H01L23/498
CPC分类号： H01L23/49541 , H01L21/50 , H01L23/043 , H01L23/3157 , H01L23/49503 , H01L23/49861 , H01L2924/0002 , H01L2924/00
摘要： An electronic package structure includes a substrate having a plurality of conductive leads. A discharge hole is disposed to extend through the substrate. An electronic chip is electrically connected to the plurality of conductive leads. A case is connected to the substrate and defines a cavity between the substrate and an upper of the case. The discharge hole and the electronic chip are disposed within the cavity, and the discharge hole is open to the outside in the electronic package structure. The discharge hole is configured to discharge air pressure that forms during the assembly process thereby improving the reliability of the electronic package structure.

46. 发明授权

US09502392B2 Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects 有权
标题翻译：具有嵌入式半导体管芯和衬底至衬底互连的半导体器件
公开(公告)号：US09502392B2
公开(公告)日：2016-11-22
申请号：US14522572
申请日：2014-10-23
申请人： Amkor Technology, Inc.
发明人： Jin Seong Kim , Ye Sul Ahn , Cha Gyu Song
IPC分类号： H01L23/48 , H01L25/10 , H01L23/498 , H01L23/538 , H01L23/00 , H01L23/31
CPC分类号： H01L23/5389 , H01L21/4853 , H01L21/486 , H01L21/565 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L24/81 , H01L25/105 , H01L2224/131 , H01L2224/16225 , H01L2225/1023 , H01L2225/1058 , H01L2225/1076 , H01L2924/12042 , H01L2924/15321 , H01L2924/15331 , H01L2924/00 , H01L2924/014
摘要： A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate.
摘要翻译：公开了一种具有嵌入式半导体管芯和衬底至衬底互连的半导体器件，其可包括具有顶表面和底表面的衬底，与衬底顶表面结合的半导体管芯，封装半导体的第一模具材料模具和衬底的顶表面的至少一部分，以及位于衬底的顶表面上并且被第一模具材料至少部分地包封的第一导电凸块。可以利用第一导电凸块将延伸的衬底耦合到衬底。第二导电凸块可以形成在衬底的底表面上，并且第二模具材料可以封装第二导电凸块的至少一部分和衬底的底表面的至少一部分。可以在第一模具材料和延伸的基板之间形成第三模具材料。

47. 发明授权

US09472494B2 Lead frame for semiconductor device 有权
标题翻译：半导体器件引线框架
公开(公告)号：US09472494B2
公开(公告)日：2016-10-18
申请号：US13466717
申请日：2012-05-08
申请人： Joon Su Kim , Jung Soo Park , Gi Jeong Kim
发明人： Joon Su Kim , Jung Soo Park , Gi Jeong Kim
IPC分类号： H01L23/48 , H01L23/495
CPC分类号： H01L23/49582 , H01L2924/0002 , H01L2924/00
摘要： Provided is a lead frame for a semiconductor device, which includes a base layer made of copper, a strike plating layer or a self assembly monolayer (SAM), thereby preventing oxidation of a base layer while simplifying the manufacturing process, reducing the manufacturing costs and reducing a failure ratio. In one embodiment, in the lead frame for a semiconductor device including a die pad and a plurality of leads positioned adjacent to each other around the die pad, the lead frame includes a base layer made of copper; and a first strike plating layer formed on the one or more portions of the surface of the base layer.
摘要翻译：提供一种半导体器件的引线框架，其包括由铜制成的基底层，触击镀层或自组装单层（SAM），从而防止了基底层的氧化，同时简化了制造工艺，降低了制造成本和降低故障率。在一个实施例中，在用于半导体器件的引线框架中，引线框架包括由铜制成的基极层，所述引线框架包括管芯焊盘和围绕管芯焊盘彼此相邻定位的多个引线，以及形成在所述基底层的所述表面的所述一个或多个部分上的第一触击镀层。

48. 发明授权

US09466580B2 Semiconductor package and manufacturing method thereof 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US09466580B2
公开(公告)日：2016-10-11
申请号：US14815435
申请日：2015-07-31
申请人： Amkor Technology, Inc.
发明人： Jong Sik Paek , No Sun Park
IPC分类号： H01L21/768 , H01L21/48 , H01L21/56 , H01L23/00 , H01L25/00 , H01L25/065
CPC分类号： H01L24/05 , H01L23/3114 , H01L24/13 , H01L24/24 , H01L24/25 , H01L24/73 , H01L24/82 , H01L25/0657 , H01L2224/022 , H01L2224/02371 , H01L2224/02375 , H01L2224/0401 , H01L2224/04105 , H01L2224/05024 , H01L2224/05569 , H01L2224/05572 , H01L2224/12105 , H01L2224/13022 , H01L2224/13023 , H01L2224/13024 , H01L2224/14131 , H01L2224/24105 , H01L2224/24146 , H01L2224/2499 , H01L2224/25175 , H01L2224/32145 , H01L2224/73217 , H01L2224/73267 , H01L2224/82 , H01L2224/8203 , H01L2224/92244 , H01L2224/94 , H01L2224/97 , H01L2224/83
摘要： A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding.
摘要翻译：半导体器件结构和半导体器件的制造方法。作为非限制性示例，本公开的各个方面提供半导体器件结构（例如，传感器器件结构）及其制造方法，其包括通过硅通孔的无接合线的三维封装结构，以及 /或倒装芯片接合。

49. 发明授权

US09431334B2 Semiconductor device having single layer substrate and method 有权
标题翻译：具有单层衬底和方法的半导体器件
公开(公告)号：US09431334B2
公开(公告)日：2016-08-30
申请号：US14593310
申请日：2015-01-09
申请人： Amkor Technology, Inc.
发明人： Hyung Il Jeon , Byong Jin Kim , Gi Jeong Kim , Jae Min Bae , Tae Ki Kim
IPC分类号： H01L23/28 , H01L23/498 , H01L21/78 , H01L21/48 , H01L23/31 , H01L25/10 , H01L25/00 , H01L23/00 , H01L21/56
CPC分类号： H01L23/49838 , H01L21/486 , H01L21/561 , H01L21/78 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L24/16 , H01L24/81 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/16227 , H01L2224/81005 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/15321 , H01L2924/1533 , H01L2924/18161 , H01L2224/81
摘要： In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the insulation layer. A semiconductor die is attached on a first surface of the single layer substrate and electrically connected to the conductive patterns. Conductive bumps are also on the first surface of the single layer substrate and electrically connected to the semiconductor die through the conductive patterns. An encapsulant overlaps at least portions of the first surface of the single layer substrate. The conductive bumps are at least partially exposed in the encapsulant.
摘要翻译：在一个实施例中，半导体器件包括在绝缘层的第一表面上具有绝缘层和导电图案的单层衬底。半导体管芯安装在单层衬底的第一表面上并电连接到导电图案。导电凸块也在单层基板的第一表面上并且通过导电图案电连接到半导体管芯。密封剂与单层基材的第一表面的至少部分重叠。导电凸块至少部分地暴露在密封剂中。

50. 发明授权

US09418942B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09418942B2
公开(公告)日：2016-08-16
申请号：US14565725
申请日：2014-12-10
申请人： Amkor Technology, Inc.
发明人： Ji Young Chung , Yoon Joo Kim , Do Hyun Na
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/12 , H01L23/053 , H01L23/34 , H01L23/28 , H01L23/538 , H01L23/00 , H01L25/10 , H01L21/56 , H01L23/552
CPC分类号： H01L23/5389 , H01L21/568 , H01L23/552 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/24 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/96 , H01L25/105 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13025 , H01L2224/131 , H01L2224/16227 , H01L2224/16235 , H01L2224/19 , H01L2224/32145 , H01L2224/73215 , H01L2224/73217 , H01L2224/8203 , H01L2224/83005 , H01L2224/92144 , H01L2225/1023 , H01L2225/1058 , H01L2225/1076 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/1815 , H01L2924/18161 , H01L2924/18162 , H01L2924/014 , H01L2924/00
摘要： In one embodiment, a semiconductor package includes a first semiconductor die having a first surface facing upwardly to expose a bond pad, a second semiconductor die having a first surface facing downwardly to expose a bond pad and disposed to be offset with the first surface of the first semiconductor die, and an encapsulant encapsulating the first semiconductor die and the second semiconductor die together. Throughholes are disposed in the encapsulant adjacent the bond pad of the first semiconductor die and adjacent the bond pad of the second semiconductor die.
摘要翻译：在一个实施例中，半导体封装包括第一半导体管芯，其具有面向上的第一表面以暴露接合焊盘;第二半导体管芯，具有面向下的第一表面以暴露接合焊盘并且设置成与第一表面相抵消第一半导体管芯和将第一半导体管芯和第二半导体管芯封装在一起的密封剂。通孔设置在与第一半导体管芯的接合焊盘相邻并且与第二半导体管芯的接合焊盘相邻的密封剂中。

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