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31. 发明授权

US5502007A Method of forming flat surface of insulator film of semiconductor device 失效
标题翻译：形成半导体器件绝缘膜平面的方法
公开(公告)号：US5502007A
公开(公告)日：1996-03-26
申请号：US283295
申请日：1994-07-28
申请人： Hiroshi Murase
发明人： Hiroshi Murase
IPC分类号： H01L21/316 , H01L21/3105 , H01L21/318 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/302 , H01L21/463
CPC分类号： H01L21/76819 , H01L21/31053
摘要： A method of forming a flat surface of an insulator film of a semiconductor device, providing no excessive polishing, polishing waste that is easily removed and an extensive flat surface of the insulator film. A first wiring film is formed on or over a semiconductor substrate and a first insulator film is formed on the first wiring film. The first insulator film and the first wiring film are patterned to a given shape in the same patterning process. A second insulator film is formed on the first insulator film thus patterned. The second insulator film is relatively higher in polishing rate than the first insulator film. Then, a surface of the second insulator film is polished to be flattened under pressure until the first insulator film is exposed. As the first and second insulator films, a silicon nitride film and a silicon dioxide film are preferably used, respectively.
摘要翻译：一种形成半导体器件的绝缘膜的平坦表面的方法，其不提供过度的抛光，抛光容易除去的废物和绝缘膜的广泛的平坦表面。第一布线膜形成在半导体衬底上或上方，并且第一绝缘膜形成在第一布线膜上。第一绝缘膜和第一布线膜在相同的图案化工艺中被图案化成给定的形状。在如此构图的第一绝缘膜上形成第二绝缘膜。第二绝缘膜的抛光速度比第一绝缘膜高。然后，第二绝缘膜的表面被抛光以在压力下变平，直到第一绝缘膜露出。作为第一和第二绝缘膜，优选分别使用氮化硅膜和二氧化硅膜。

32. 发明授权

US5461007A Process for polishing and analyzing a layer over a patterned semiconductor substrate 失效
标题翻译：用于抛光和分析图案化半导体衬底上的层的工艺
公开(公告)号：US5461007A
公开(公告)日：1995-10-24
申请号：US253013
申请日：1994-06-02
申请人： Thomas S. Kobayashi
发明人： Thomas S. Kobayashi
IPC分类号： H01L21/66 , B24B37/013 , B24B49/02 , G01B11/02 , G01B11/30 , H01L21/304 , H01L21/302 , H01L21/463
CPC分类号： B24B37/013 , B24B49/02 , G01B11/028 , G01B11/303
摘要： A layer over a patterned semiconductor is polished and analyzed to determine a polishing endpoint. The analysis may be performed using reflected radiation beams or by a radiation scattering analyzer. The analysis may be performed on virtually any layer using a radiation source. The analysis may be performed with a liquid, such as an aqueous slurry, contacting the substrate. The polishing and analysis may be integrated such that both steps are performed on the same polisher.
摘要翻译：抛光和分析图案化半导体上的层以确定抛光终点。可以使用反射辐射束或通过辐射散射分析仪进行分析。可以在几乎任何使用辐射源的层上进行分析。该分析可以用与底物接触的液体，例如含水浆料进行。抛光和分析可以被整合，使得两个步骤在相同的抛光机上进行。

33. 发明授权

US5445996A Method for planarizing a semiconductor device having a amorphous layer 失效
标题翻译：用于平坦化具有非晶层的半导体器件的方法
公开(公告)号：US5445996A
公开(公告)日：1995-08-29
申请号：US66375
申请日：1993-05-25
申请人： Masako Kodera , Hiroyuki Yano , Atsushi Shigeta , Riichirou Aoki , Hiromi Yajima , Haruo Okano
发明人： Masako Kodera , Hiroyuki Yano , Atsushi Shigeta , Riichirou Aoki , Hiromi Yajima , Haruo Okano
IPC分类号： B24B37/04 , B24B49/00 , B24B49/02 , B24B49/04 , B24B49/16 , C09K3/14 , H01L21/3105 , H01L21/66 , H01L21/768 , H01L21/302 , H01L21/463
CPC分类号： B24B37/013 , B24B37/04 , B24B49/00 , B24B49/02 , B24B49/04 , B24B49/16 , C09K3/1463 , H01L21/31051 , H01L21/31053 , H01L21/76819 , H01L22/26 , H01L2924/0002
摘要： To planarize an insulating film formed on a semiconductor substrate, a polishing slurry containing cerium oxide is used to polish the surface of the insulating film. Using the cerium oxide included slurry as a polishing agent, the insulating film is not contaminated by alkali metals during the polishing process. Furthermore, the insulating film is polished at an enhanced polishing rate.
摘要翻译：为了平坦化形成在半导体衬底上的绝缘膜，使用含有氧化铈的抛光浆料来抛光绝缘膜的表面。使用包含二氧化铈的浆料作为抛光剂，在抛光过程中绝缘膜不被碱金属污染。此外，以增强的抛光速率对绝缘膜进行抛光。

34. 发明授权

US5275976A Process chamber purge module for semiconductor processing equipment 失效
标题翻译：用于半导体加工设备的处理室吹扫模块
公开(公告)号：US5275976A
公开(公告)日：1994-01-04
申请号：US634676
申请日：1990-12-27
申请人： Mehrdad M. Moslehi
发明人： Mehrdad M. Moslehi
IPC分类号： H01L21/205 , C23C16/48 , C30B25/10 , C30B31/12 , C30B31/16 , H01L21/00 , H01L21/26 , H01L21/31 , H01L21/324 , H01L21/02 , H01L21/302 , H01L21/463
CPC分类号： H01L21/67017 , C23C16/481 , C30B25/105 , C30B31/12 , C30B31/16 , Y10S438/905 , Y10S438/909
摘要： A process chamber purge module (56) is provided, including a stack module (60) and a process chamber liner (62). The stack module comprises a plurality of quartz plates (100, 110, and 116) having flow apertures to permit radial and axial flow of a purge gas to the backside of a semiconductor wafer (18). The process chamber liner (62) isolates the process chamber walls from the process chamber process environment by flowing between the liner and the walls a portion of the purge gas. Process chamber liner (62) comprises a quartz cylindrical collar that operates to decouple the process chamber (16) process environment (20) from the process chamber collar walls (42). The stack module (60) decouples the process chamber optical/vacuum quartz window (64) from the semiconductor wafer (18) during a heated semiconductor wafer fabrication process. By flowing purge gas to the backside of the semiconductor wafer (18), the present invention prevents reactive process gas interaction with the semiconductor wafer backside.
摘要翻译：提供了一种处理室净化模块（56），其包括堆叠模块（60）和处理室衬垫（62）。堆叠模块包括多个具有流动孔的石英板（100,110和116），以允许吹扫气体向半导体晶片（18）的背面径向和轴向流动。处理室衬套（62）通过在衬套和壁之间流动吹扫气体的一部分来隔离处理室壁与处理室工艺环境。处理室衬套（62）包括石英圆柱形套环，其操作以将处理室（16）处理环境（20）与处理室套环壁（42）分离。堆叠模块（60）在加热的半导体晶片制造过程期间将处理室光学/真空石英窗口（64）与半导体晶片（18）分离。通过将清洗气体流到半导体晶片（18）的背面，本发明防止与半导体晶片背面的反应性工艺气体相互作用。

35. 发明授权

US4704369A Method of severing a semiconductor device 失效
标题翻译：切断半导体器件的方法
公开(公告)号：US4704369A
公开(公告)日：1987-11-03
申请号：US718770
申请日：1985-04-01
申请人： Prem Nath , Avtar Singh
发明人： Prem Nath , Avtar Singh
IPC分类号： H01L31/04 , H01L21/205 , H01L21/301 , H01L21/302 , H01L31/20 , H01L21/463
CPC分类号： H01L21/302 , H01L31/206 , Y02E10/50 , Y02P70/521 , Y10T83/0562
摘要： An improved method for severing a large area semiconductor device, including a substrate having a base electrode region thereupon, semiconductor body and top electrode into smaller area devices includes the steps of supporting the semiconductor device from the top electrode side thereof and applying a cutting force to the substrate side of the semiconductor device so as to cut the device without establishing short circuit contact between the substrate electrode and the top electrode thereof. Also included is a large area semiconductor device having a protective layer affixed to the top electrode surface thereof. The large area device is readily adapted for severing into smaller area photovoltaic devices by the method disclosed herein.
摘要翻译：一种用于切断大面积半导体器件的改进方法，包括其上具有基极电极区域的衬底，半导体本体和顶部电极到更小面积的器件中的方法包括以下步骤：从其顶部电极侧支撑半导体器件，并将切割力施加到半导体器件的衬底侧，以便切断器件而不会在衬底电极及其顶部电极之间建立短路接触。还包括具有固定在其顶电极表面上的保护层的大面积半导体器件。通过本文公开的方法，大面积装置容易适应于切割成更小面积的光伏器件。

36. 发明公开

US20240379374A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20240379374A1
公开(公告)日：2024-11-14
申请号：US18780440
申请日：2024-07-22
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hung-Pin Chang , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L21/3105 , H01L21/02 , H01L21/027 , H01L21/3065 , H01L21/463
CPC分类号： H01L21/31055 , H01L21/0273 , H01L21/3065 , H01L21/463 , H01L21/02063
摘要： A manufacturing method of a semiconductor structure includes: forming a liner structure on an inner sidewall of a dielectric layer overlying a semiconductor substrate; forming a via hole in an area of the semiconductor substrate which is exposed by the liner structure, wherein an overhang portion of the semiconductor substrate having a tapering arc-shaped profile and overhanging the via hole is formed; and filling the via hole with a conductive material.

37. 发明公开

US20240194492A1 SEPARATION METHOD OF BONDED SUBSTRATES 审中-公开
公开(公告)号：US20240194492A1
公开(公告)日：2024-06-13
申请号：US18076979
申请日：2022-12-07
申请人： SKY TECH INC.
发明人： JUNG-HUA CHANG , JING-CHENG LIN , TA-HAO KUO
IPC分类号： H01L21/463 , H01L21/02 , H01L21/677 , H01L21/68 , H01L21/683 , H01L21/687
CPC分类号： H01L21/463 , H01L21/02052 , H01L21/67706 , H01L21/67718 , H01L21/68 , H01L21/6835 , H01L21/6838 , H01L21/68721
摘要： The disclosure is a separation method of bonded substrates. The bonded substrate is placed on a breathable plate of a debonding device to separate a wafer and a carrier substrate of the bonded substrate, and the wafer is placed on the breathable plate. A robot arm moves the wafer and the breathable plate to a cleaning device for cleaning, and then moves the wafer and the breathable plate to a relay device. Clamping units of the relay device clamp the breathable plate, and a bernoulli arm sucks the wafer and separates the wafer and the breathable plate, and then the robot arm transports the wafer and the breathable plate to a storage device respectively. The disclosure can automatically debond and clean the bonded substrate, and automatically move the wafer from the breathable plate, which can avoid the fragmentation of wafer.

38. 发明授权

US11776966B2 Semiconductor device and method for manufacturing the semiconductor device 有权
公开(公告)号：US11776966B2
公开(公告)日：2023-10-03
申请号：US17329250
申请日：2021-05-25
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Ryota Hodo , Motomu Kurata , Shinya Sasagawa , Satoru Okamoto , Shunpei Yamazaki
IPC分类号： H01L27/12 , H01L29/786 , H01L29/66 , H01L21/467 , H01L21/463 , H01L21/768 , H01L21/02 , H01L23/522 , H01L23/532 , H01L29/778
CPC分类号： H01L27/1225 , H01L21/02565 , H01L21/463 , H01L21/467 , H01L21/76895 , H01L23/5226 , H01L23/53295 , H01L27/1288 , H01L29/66969 , H01L29/7869 , H01L29/78603 , H01L29/78648 , H01L29/78696 , H01L23/53238 , H01L29/7781 , H01L29/7782
摘要： First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

39. 发明申请

US20220028700A1 GALLIUM OXIDE SUBSTRATE AND METHOD OF MANUFACTURING GALLIUM OXIDE SUBSTRATE 有权
公开(公告)号：US20220028700A1
公开(公告)日：2022-01-27
申请号：US17493082
申请日：2021-10-04
申请人： AGC Inc.
发明人： Yusuke HIRABAYASHI
IPC分类号： H01L21/463 , H01L29/34 , H01L29/24 , C01G15/00 , C30B29/16
摘要： A gallium oxide substrate includes first and second main surfaces. When measured data z0(r,θ) of height differences of points (r,θ,z) on the first main surface from a least square plane of the first main surface are approximated by a function z(r,θ)=Σanmznm(r,θ), a ratio of a first maximum height difference of a component of z(r,θ) obtained by summing terms anmznm(r,θ) with an index j of 4, 9, 16, 25, 36, 49, 64, and 81, when the second main surface is placed facing a horizontal flat surface, to a diameter of the first main surface is 0.39×10−4 or less, and a ratio of a second maximum height difference of a component of z(r,θ) obtained by summing terms anmznm(r,θ) with j of from 4 to 81, when an entire surface of the second main surface is adsorbed to a flat chuck surface, to the diameter is 0.59×10−4 or less.

40. 发明授权

US11227812B2 Package and manufacturing method thereof 有权
公开(公告)号：US11227812B2
公开(公告)日：2022-01-18
申请号：US16745355
申请日：2020-01-17
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ming-Fa Chen , Sung-Feng Yeh , Jian-Wei Hong
IPC分类号： H01L23/48 , H01L23/31 , H01L23/544 , H01L25/00 , H01L21/768 , H01L21/463 , H01L25/065 , H01L21/56
摘要： A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, a first through insulating via (TIV), and a second TIV. The semiconductor carrier has a contact via embedded therein. The contact via is electrically grounded. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The first TIV is aside the first die. The first TIV penetrates through the first encapsulant and is electrically connected to the contact via. The second TIV is aside the second die. The second TIV penetrates through the second encapsulant and is electrically connected to the contact via and the first TIV.

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