专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US5359718A Early scalable instruction set machine alu status prediction apparatus 失效
标题翻译：早期可扩展指令集机ALU状态预测装置
公开(公告)号：US5359718A
公开(公告)日：1994-10-25
申请号：US677692
申请日：1991-03-29
申请人： James E. Phillips , Stamatis Vassiliadis
发明人： James E. Phillips , Stamatis Vassiliadis
IPC分类号： G06F7/575 , G06F7/38 , G06F7/50
CPC分类号： G06F7/575 , G06F7/4991
摘要： An apparatus implementing an algorithm for generating carries due to the second instruction of an interlocked instruction pair when executing all combinations of logical as well as arithmetic instruction pairs is developed. The algorithm is then applied to three interlock collapsing ALU means implementations that have been proposed. The critical path for calculating the carries is first presented. Next the expression for generating these carries is used to derive a fast implementation for generating overflow which is implemented in the apparatus. The resulting ALU status determination apparatus includes a three-to-one ALU means for executing plural instructions which can predict the status of three-to-one ALU operations related to the presence/absence of carries incorporated in the three-to-one ALU designed to execute a second instruction of a pair of instructions in parallel and whether or not the second instruction of the pair is independent or dependent on the result of the operation of the first instruction. Additionally, an implementation scheme for predicting result equal to zero is developed for the three-to-one ALU operations.
摘要翻译：开发了执行逻辑和算术指令对的所有组合时由于互锁指令对的第二指令而产生运算的算法的装置。该算法然后被应用于已经提出的三个互锁折叠ALU装置实现。首先介绍了运算计算的关键路径。接下来，用于产生这些载体的表达式用于导出在装置中实现的用于产生溢出的快速实现。所得到的ALU状态确定装置包括用于执行多个指令的三对一ALU装置，其可以预测与设计的三对一ALU中包含的载体的存在/不存在相关的三对一ALU操作的状态并行执行一对指令的第二指令，以及该对的第二指令是否是独立的或取决于第一指令的操作结果。另外，为三对一ALU操作开发了一种用于预测结果等于零的实现方案。

32. 发明授权

US5299319A High performance interlock collapsing SCISM ALU apparatus 失效
标题翻译：高性能互锁倒塌SCISM ALU设备
公开(公告)号：US5299319A
公开(公告)日：1994-03-29
申请号：US677079
申请日：1991-03-29
申请人： Stamatis Vassiliadis , James E. Phillips
发明人： Stamatis Vassiliadis , James E. Phillips
IPC分类号： G06F7/00 , G01N33/04 , G01N33/44 , G06F7/50 , G06F7/508 , G06F7/575 , G06F9/302 , G06F9/38 , G06F15/20 , G06F9/40
CPC分类号： G06F7/575 , G06F9/3001 , G06F9/3836 , G06F9/3853 , G06F7/4991
摘要： Three high performance implementations for an interlock collapsing ALU are presented as alternative embodiments. The critical path delay of each embodiment provides reduction in delay. For one of the implementations the delay is shown to be an equivalent number of stages as required by a three-to-one adder assuming a commonly available bookset. The delay for the other two implementations is comparable to the three-to-one adder. In addition, trade-offs for the design complexity of implementation alternatives are set out. The embodiments achieve minimum delays without a prohibitive increase in hardware.
摘要翻译：作为替代实施例，呈现了用于互锁折叠ALU的三个高性能实现。每个实施例的关键路径延迟提供了延迟的减少。对于其中一个实施方案，延迟被显示为假设一个通用可用的书集所要求的三对一加法器的等效数量级。其他两个实现的延迟与三对一加法器相当。此外，还规定了替代方案的设计复杂性的权衡。这些实施例实现最小延迟，而不会在硬件上增加禁止。

33. 发明授权

US5227989A Arithmetic logic unit for microprocessor with sign bit extend 失效
标题翻译：具有符号位延迟的微处理器的算术逻辑单元
公开(公告)号：US5227989A
公开(公告)日：1993-07-13
申请号：US770043
申请日：1991-09-30
申请人： Morris E. Jones, Jr. , James A. Picard
发明人： Morris E. Jones, Jr. , James A. Picard
IPC分类号： G06F7/575
CPC分类号： G06F7/575 , G06F2207/3828 , G06F7/49994
摘要： An arithmetic logic unit for a microprocessor is shown and described for use in a 24-bit data path where the ALU includes three separate ALU portions, one for each byte of the data path, and three separate control signals, one for each portion of the ALU. The ALU provides a variety of arithmetic and logic functions for application to 24-bit operands, but also includes a capability of manipulating such operands in accordance with sign extended opcodes without actually physically executing a sign extend operation within the microprocessor. In this manner, the ALU executes the necessary logic functions to provide the same ultimate result as sign bit extension, but does not require a separate sign bit extension step within the microprocessor to convert signed byte operand into a signed word operand.
摘要翻译：用于微处理器的算术逻辑单元被示出和描述用于24位数据路径，其中ALU包括三个单独的ALU部分，一个用于数据路径的每个字节，以及三个单独的控制信号，一个用于 ALU。 ALU为应用于24位操作数提供了各种算术和逻辑功能，但也包括根据符号扩展操作码操作这些操作数的功能，而不会在微处理器内实际执行符号扩展操作。以这种方式，ALU执行必要的逻辑功能以提供与符号位扩展相同的最终结果，但是在微处理器内不需要单独的符号位扩展步骤来将有符号字节操作数转换为有符号字操作数。

34. 发明授权

US5224065A Arithmetic operation unit having bit inversion function 失效
标题翻译：具有位反转功能的算术运算单元
公开(公告)号：US5224065A
公开(公告)日：1993-06-29
申请号：US814719
申请日：1991-12-30
申请人： Makoto Yoshida
发明人： Makoto Yoshida
IPC分类号： G06F7/501 , G06F7/50 , G06F7/503 , G06F7/506 , G06F7/575
CPC分类号： G06F7/503 , G06F7/575 , G06F2207/3852
摘要： A bit-inversion arithmetic operation unit comprises a first carry signal line for propagating a carry signal from a more significant bit position side to a less significant bit position side, and a second carry signal line for propagating a carry signal from a less significant bit position side to a more significant bit position side. A common logic circuit performs at least a portion of a carry control including a carry propagation of the first and second carry signals and a carry generation. A switching and logic circuit responds to a required arithmetic operation mode so as to control the common logic circuit and to perform the remaining portion of the carry control including the carry propagation of the first and second carry signals and the carry generation.

35. 发明授权

US5206940A Address control and generating system for digital signal-processor 失效
标题翻译：数字信号处理器的地址控制和发生系统
公开(公告)号：US5206940A
公开(公告)日：1993-04-27
申请号：US750512
申请日：1991-08-27
申请人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
发明人： Tokumichi Murakami , Koh Kamizawa , Yoshiaki Katoh , Hideo Ohira , Masatoshi Kameyama , Naoto Kinjo
IPC分类号： G06F7/575 , G06F9/32 , G06F9/355 , G06F9/38 , G06F13/28 , G06F15/78
CPC分类号： G06F7/575 , G06F13/28 , G06F15/7832 , G06F15/7842 , G06F15/786 , G06F9/30058 , G06F9/30094 , G06F9/355 , G06F9/3877 , G06F9/3885 , G06F2207/3884
摘要： A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.
摘要翻译：一种简单的电路配置的数字信号处理器，其能够以高处理速度以减少的步数有效地实现算术处理和中断处理。数字信号处理器包括指令执行流水线级，包括从数据存储器读取数据并将数据应用于运算单元的阶段; 用于执行级的运算单元，包括桶形移位器，乘法器和算术和逻辑单元，归一化桶形移位器，舍入/累积加法器，用于写入/累加级的内部数据存储器和DMA传输总线，地址产生单元，其能够并行和二维地生成两个输入，一个输出数据存储器地址和用于控制通过内部数据存储器之间的DMA总线和用于指令的外部数据存储器的二维数据传输的DMA控制单元执行阶段

36. 发明授权

US4888722A Parallel arithmetic-logic unit for as an element of digital signal processor 失效
标题翻译：用作数字信号处理器元件的并行算术逻辑单元
公开(公告)号：US4888722A
公开(公告)日：1989-12-19
申请号：US69431
申请日：1987-07-02
申请人： Charles P. Boreland
发明人： Charles P. Boreland
IPC分类号： G06F7/575
CPC分类号： G06F7/575
摘要： A parallel arithmetic-logic unit (PALU) controlled by a microinstruction sequencer and capable of executing conditional operations in a single pass is disclosed. The PALU generally comprises first and second registers for storing data, a comparator for continually comparing the values in the registers, and an arithmetic-logic core connected to the registers for performing arithmetic, logical and data move operations on the data in the registers. The comparator is preferably an unsigned magnitude comparator which outputs flags indicative of the relative status of the values in the registers. The flags are read by a microinstruction sequencer which then uses the flag information to determine what operation the arithmetic-logic core is to conduct. Preferably, a shifter is also provided between one of the registers and the arithmetic-logic core.

37. 发明授权

US4815019A Fast ALU equals zero circuit 失效
标题翻译：快速ALU等于零电路
公开(公告)号：US4815019A
公开(公告)日：1989-03-21
申请号：US19101
申请日：1987-02-26
申请人： Patrick W. Bosshart
发明人： Patrick W. Bosshart
IPC分类号： G06F7/02 , G06F7/575 , G06F7/38
CPC分类号： G06F7/575 , G06F7/02
摘要： A fast ALU=0 circuit is used with a carry-select lookahead ALU. Preliminary ALU=0 signals are derived for each section of the ALU prior to a carry in signal being received by that section. When the carry in signal is received, a final comparison is made with the least significant bit of the section and the final ALU=0 signal generated. The ALU=0 computation is complete one gate delay after the ALU computation is complete.
摘要翻译：快速ALU = 0电路与进位选择前视图ALU一起使用。在由该部分接收到进位信号之前，对ALU的每个部分导出初步ALU = 0信号。当接收到进位信号时，最后比较该部分的最低有效位，并产生最终的ALU = 0信号。在ALU计算完成之后，ALU = 0计算完成一个门延迟。

38. 发明授权

US4810995A Arithmetic and logic operating unit 失效
标题翻译：算术逻辑运算单元
公开(公告)号：US4810995A
公开(公告)日：1989-03-07
申请号：US21666
申请日：1987-02-09
申请人： Harufusa Kondou , Hideki Ando
发明人： Harufusa Kondou , Hideki Ando
IPC分类号： G06F7/02 , G06F7/38 , G06F7/508 , G06F7/575 , H03M1/34 , H03M5/18
CPC分类号： G06F7/575 , H03M5/18 , G06F7/49921
摘要： An arithmetic and logic unit control circuit includes arithmetic circuits (10a-10d) for generating the absolute value .vertline.A.vertline. of an input signal A and the complement B of an input signal B from n-bit input signals A and B in response to a control signal from a controller (14). Full adders (6a-6d) add outputs from the arithmetic circuits in response to a control signal from the controller (14). First logic circuits (20a-20c, 21) extract the most significant bit of (.vertline.A.vertline.-B) to form outputs of the full adders (6a-6d) in response to a control signal from controller (14) and second logic circuits (20e, 21) to perform a three-level decision of values A and B from the outputs of the first logic circuits (20a-20c, 21) and the most significant bit of the input signal A. The arithmetic and logic unit can thereby perform Alternate Mark Inversion (AMI) coding in one machine cycle.
摘要翻译：算术和逻辑单元控制电路包括用于根据来自n位输入信号A和B的输入信号A的输入信号B的绝对值| A |和输入信号B的补码和上升＆amp; B的运算电路（10a-10d）响应于来自控制器（14）的控制信号。响应于来自控制器（14）的控制信号，全加器（6a-6d）从运算电路添加输出。响应于来自控制器（14）和第二逻辑电路（14）的控制信号，第一逻辑电路（20a-20c，21）提取（| A|-B）的最高有效位以形成全加器（6a-6d）的输出（20e，21）从第一逻辑电路（20a-20c，21）的输出和输入信号A的最高有效位执行值A和B的三电平判定。由此算术和逻辑单元在一个机器周期中执行替代标记反转（AMI）编码。

39. 发明授权

US4706209A Arithmetic and logic unit with overflow indicator 失效
标题翻译：具有溢出指示器的算术逻辑单元
公开(公告)号：US4706209A
公开(公告)日：1987-11-10
申请号：US696910
申请日：1985-01-31
申请人： Andre Picco
发明人： Andre Picco
IPC分类号： G06F7/38 , G06F7/00 , G06F7/499 , G06F7/575 , G06F7/50
CPC分类号： G06F7/575 , G06F7/4991
摘要： The invention concerns the overflow test circuit of an arithmetic and logic unit. The circuit described does not require receiving an indication on the operating in addition or subtraction of the ALU; it receives simply the carrying input the carrying and the result output of the cell of the highest rank of the ALU: and it supplies a positive overflow signal or a negative overflow signal, when the result of the addition or subtraction of two numbers exceeds the capacity of the ALU. Two gates with three inputs and three inverters are sufficient to establish the overflow test circuit.
摘要翻译：本发明涉及算术和逻辑单元的溢出测试电路。所描述的电路不需要接收关于ALU的加法或减法的操作的指示; 它只接收携带输入的ALU的最高级别的单元的携带和结果输出，并且当两个数字的相加或减去的结果超过容量时，它提供正的溢出信号或负的溢出信号的ALU。具有三个输入和三个反相器的两个门足以建立溢出测试电路。

40. 发明授权

US4644489A Multi-format binary coded decimal processor with selective output formatting 失效
标题翻译：具有选择性输出格式的多格式二进制编码十进制处理器
公开(公告)号：US4644489A
公开(公告)日：1987-02-17
申请号：US579091
申请日：1984-02-10
申请人： Richard R. Curtin , Paul M. Clemente
发明人： Richard R. Curtin , Paul M. Clemente
IPC分类号： G06F7/38 , G06F5/00 , G06F7/00 , G06F7/48 , G06F7/491 , G06F7/493 , G06F7/575
CPC分类号： G06F7/491 , G06F7/575
摘要： Digital circuitry performs arithmetic operations upon first and second binary coded decimal digit strings input thereto. The digital circuitry provides for receiving and storing a first and second BCD digit, the digits having an arbitrary data type format. The first and second data types are selected from the group of packed and unpacked data. The circuitry then performs the arithmetic operation upon the stored BCD digits to obtain a result data word which is made available in a data type format corresponding to a selected one of the input BCD digits. In a particular embodiment, a plurality of the circuits can be operated in a digit slice structure. The digit slice structure operates upon strings of packed, unpacked, and mixed data type arithmetic operands and provides, at its output lines, output data in a format corresponding to a selected input data type. In particular, a unique interconnection of the plural output lines of the circuitry enables the output data type to be packed or unpacked as desired. The circuitry also provides for automatic selection of digits applied to the circuitry thereby relieving the operating environment from significant time consuming and costly supervision.
摘要翻译：数字电路对输入到其的第一和第二二进制编码十进制数字串进行算术运算。数字电路提供接收和存储第一和第二BCD数字，这些数字具有任意的数据类型格式。第一和第二数据类型是从打包和解压缩数据组中选择的。然后，电路对所存储的BCD数字执行算术运算，以获得结果数据字，该结果数据字以对应于输入BCD数字中所选择的一个的数据类型格式可用。在特定实施例中，多个电路可以以数字切片结构操作。数字切片结构对打包的，未打包的和混合的数据类型的算术运算符的串进行操作，并且在其输出行提供与所选择的输入数据类型对应的格式的输出数据。特别地，电路的多个输出线的独特互连使得输出数据类型能够根据需要被打包或解包。电路还提供自动选择应用于电路的数字，从而减轻操作环境的耗时和昂贵的监督。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式