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31. 发明授权

US08964578B2 Overload protection of a transformer loaded line driver 有权
标题翻译：变压器负载线路驱动器的过载保护
公开(公告)号：US08964578B2
公开(公告)日：2015-02-24
申请号：US13087027
申请日：2011-04-14
申请人： Kenneth C. Dyer
发明人： Kenneth C. Dyer
IPC分类号： H04L12/26 , H04B3/32 , G06F1/10 , H03L7/00 , H04J3/06
CPC分类号： H04L47/6245 , G06F1/10 , H03L7/00 , H04B3/32 , H04J3/0697 , H04L25/0278 , H04L43/16 , H04L47/25 , H04L47/521 , H04L47/6215 , H04L47/722
摘要： A line driver circuit an method for protecting the line driver circuit from overdrive that includes generating an output signal for a transformer coupled to a load, and comparing a voltage of the output signal to a threshold voltage value. If the comparison indicates overload, the method further includes generating a control signal to reduce an amplitude of the output signal.
摘要翻译：一种线路驱动器电路，用于保护线路驱动器电路免受过驱动，其包括产生耦合到负载的变压器的输出信号，以及将输出信号的电压与阈值电压值进行比较。如果比较指示过载，则该方法还包括产生控制信号以减小输出信号的幅度。

32. 发明授权

US08904023B2 Streaming method and system for fibre channel network devices 有权
标题翻译：光纤通道网络设备的流式传输方法和系统
公开(公告)号：US08904023B2
公开(公告)日：2014-12-02
申请号：US13312068
申请日：2011-12-06
申请人： Keith M. Arroyo , Stephen K. Wilson
发明人： Keith M. Arroyo , Stephen K. Wilson
IPC分类号： G06F15/16 , H04L29/08 , H04L12/861 , G06F3/06
CPC分类号： H04L49/9005 , G06F3/0626 , G06F3/0659 , G06F3/067 , H04L45/60 , H04L47/6245 , H04L49/90 , H04L67/1097 , H04L69/18
摘要： A system and method are disclosed for processing commands to network target devices through a SCSI router in a Fiber Channel network having a plurality of Fiber Channel hosts. The system may be configured to receive a command, and determine that the command requires a transfer of data larger than a threshold size. The system may also be configured to receive a plurality of data blocks associated with the command, store the plurality of data blocks in at least one buffer, and determine if there is an initial amount of data in the at least one buffer. The system may be further configured to forward at least one of the plurality data blocks, and request an additional data block associated with the command.
摘要翻译：公开了一种用于处理通过具有多个光纤通道主机的光纤通道网络中的SCSI路由器来对目标设备进行网络的命令的系统和方法。该系统可以被配置为接收命令，并且确定该命令需要大于阈值大小的数据传送。系统还可以被配置为接收与命令相关联的多个数据块，将多个数据块存储在至少一个缓冲器中，并且确定在至少一个缓冲器中是否存在初始数据量。该系统还可以被配置为转发多个数据块中的至少一个，并且请求与该命令相关联的附加数据块。

33. 发明申请

US20140307746A1 Method and Apparatus for Providing Timing Analysis for Packet Streams Over Packet Carriers 有权
标题翻译：用于提供分组载波上的分组流的时序分析的方法和装置
公开(公告)号：US20140307746A1
公开(公告)日：2014-10-16
申请号：US13861187
申请日：2013-04-11
申请人： TELLABS OPERATIONS, INC.
发明人： Anthony Leonard Sasak , Christopher V. O'Brien
IPC分类号： H04J3/06
CPC分类号： H04L47/283 , H04J3/0632 , H04J3/065 , H04J3/14 , H04L41/064 , H04L43/106 , H04L47/621 , H04L47/6245
摘要： A network device such as a router or switch, in one embodiment, includes a timing analyzer which is capable of providing timing analysis over one or more network circuits. The timing analyzer, in one aspect, receives a data packet traveling across a circuit emulation service (“CES”) circuit such as T1 or E1 circuit. Upon obtaining an arrival timestamp associated with the data packet, the arrival timestamp is stored in a timestamp buffer in accordance with a first-in first-out (“FIFO”) storage sequence. After identifying the oldest arrival timestamp in the timestamp buffer, an offset is generated based on the result of comparison between the arrival timestamp and the oldest timestamp. The timing analyzer can also be configured to generate timing reports on-demand based on generated offset(s).
摘要翻译：在一个实施例中，诸如路由器或交换机之类的网络设备包括能够在一个或多个网络电路上提供定时分析的定时分析器。定时分析器在一个方面接收跨越诸如T1或E1电路的电路仿真服务（“CES”）电路行进的数据分组。在获得与数据分组相关联的到达时间戳时，根据先进先出（“FIFO”）存储顺序将到达时间戳存储在时间戳缓冲器中。在识别时间戳缓冲区中最早到达时间戳之后，基于到达时间戳和最早时间戳之间的比较结果生成偏移量。定时分析器还可以被配置为基于生成的偏移来按需生成定时报告。

34. 发明授权

US08837504B2 Relay apparatus and output control method 有权
标题翻译：继电器和输出控制方式
公开(公告)号：US08837504B2
公开(公告)日：2014-09-16
申请号：US12614152
申请日：2009-11-06
申请人： Atsushi Shinozaki
发明人： Atsushi Shinozaki
IPC分类号： H04L12/28 , H04L12/861 , H04L12/835 , H04L12/869 , H04L12/863 , H04L12/801 , H04L12/823
CPC分类号： H04L47/30 , H04L47/10 , H04L47/12 , H04L47/32 , H04L47/58 , H04L47/6245 , H04L49/90 , H04L49/9078
摘要： A buffer temporarily stores data received from a network by a receiving unit. An output mode switching unit switches the mode in which the data received by the receiving unit is output to the buffer, between FIFO and FILO, in accordance with the storage amount of data temporarily stored in the buffer. For example, if the data temporarily stored in the buffer falls below a given threshold value of the buffer, data is stored in the buffer in FIFO. If the data temporarily stored in the buffer exceeds a given threshold value of the buffer, data is stored in the buffer in FILO. A sending unit outputs data taken from the buffer in FIFO or FILO, to a network.
摘要翻译：缓冲器临时存储由接收单元从网络接收的数据。输出模式切换单元根据临时存储在缓冲器中的数据的存储量，将接收单元接收到的数据输出到FIFO和FILO之间的缓冲器的模式切换。例如，如果临时存储在缓冲器中的数据低于缓冲器的给定阈值，则将数据存储在FIFO中的缓冲器中。如果临时存储在缓冲区中的数据超过缓冲区的给定阈值，则数据将存储在FILO中的缓冲区中。发送单元将从FIFO或FILO中的缓冲器获取的数据输出到网络。

35. 发明申请

US20130034086A1 SYSTEM AND METHODS FOR SYNCHRONIZING EDGE DEVICES ON CHANNELS WITHOUT CARRIER SENSE 有权
标题翻译：用于在没有载波信号的情况下同步信道上的边缘设备的系统和方法
公开(公告)号：US20130034086A1
公开(公告)日：2013-02-07
申请号：US13566481
申请日：2012-08-03
申请人： Marcia R. MARTIN , Henrick F. BERNHEIM , Andrew Louis ABENDSCHEIN
发明人： Marcia R. MARTIN , Henrick F. BERNHEIM , Andrew Louis ABENDSCHEIN
IPC分类号： H04L7/04 , H04W72/04 , H04W56/00
CPC分类号： H04W74/0891 , H04L7/04 , H04L41/5022 , H04L47/6245 , H04W28/065 , H04W56/00
摘要： A system and method are disclosed for synchronizing edge devices on a network, wherein the network has limited bandwidth and does not support a practical carrier sense mechanism. The edge devices transmit, using a slotted protocol, to a server located at a central data aggregation point. The server also controls a Central Transmitter, which sends messages to the edge devices to assign transmission slots and provide timing information to the edge devices to ensure that transmissions sent by devices sharing the same communication channel do not collide.
摘要翻译：公开了一种用于同步网络上的边缘设备的系统和方法，其中网络具有有限的带宽并且不支持实际的载波侦听机制。边缘设备使用时隙协议发送到位于中央数据聚合点的服务器。服务器还控制中央发射机，其向边缘设备发送消息以分配传输时隙，并向边缘设备提供定时信息，以确保共享相同通信信道的设备发送的传输不会发生冲突。

36. 发明申请

US20120230348A1 DATA BLOCKING SYSTEMS FOR NON-ARBITRARY NETWORKS 有权
标题翻译：非仲裁网络的数据阻塞系统
公开(公告)号：US20120230348A1
公开(公告)日：2012-09-13
申请号：US13415112
申请日：2012-03-08
申请人： Donald Pannell
发明人： Donald Pannell
IPC分类号： H04J3/16
CPC分类号： H04L47/6215 , H04J3/0635 , H04L47/245 , H04L47/283 , H04L47/6235 , H04L47/6245 , H04L49/901
摘要： A network device includes a memory with a first queue and a second queue. A timing module generates a first priority timing signal or a second priority timing signal based on a clock signal. The clock signal is shared between the network device and other network devices in a non-arbitrary network. The network device includes a deblocking shaper or a blocking shaper. The deblocking shaper (i) forwards first protected data from the first queue, and (ii) generates a deblocking signal based on a first frame signal and the first priority timing signal. The blocking shaper (i) forwards one of second protected data and unprotected data from the second queue, and (ii) generates a first blocking signal based on a second frame signal and the second priority timing signal. A selector module selects the first frame or the second frame based on the deblocking signal and the first blocking signal.
摘要翻译：网络设备包括具有第一队列和第二队列的存储器。定时模块基于时钟信号产生第一优先级定时信号或第二优先级定时信号。时钟信号在网络设备和非任意网络中的其他网络设备之间共享。网络设备包括去块整形器或阻塞整形器。解块整形器（i）从第一队列转发第一受保护数据，以及（ii）基于第一帧信号和第一优先级定时信号产生去块信号。阻塞整形器（i）从第二队列转发第二受保护数据和未受保护数据中的一个，以及（ii）基于第二帧信号和第二优先级定时信号产生第一阻塞信号。选择器模块基于去块信号和第一阻塞信号来选择第一帧或第二帧。

37. 发明申请

US20120155342A1 HYBRID FREQUENCY COMPENSATION NETWORK 有权
标题翻译：混合频率补偿网络
公开(公告)号：US20120155342A1
公开(公告)日：2012-06-21
申请号：US13406788
申请日：2012-02-28
申请人： Patrick Isakanian , Kenneth C. Dyer
发明人： Patrick Isakanian , Kenneth C. Dyer
IPC分类号： H04B1/58
CPC分类号： H04L47/6245 , G06F1/10 , H03L7/00 , H04B3/32 , H04J3/0697 , H04L25/0278 , H04L43/16 , H04L47/25 , H04L47/521 , H04L47/6215 , H04L47/722
摘要： Hybrid frequency compensation is provided. Hybrid circuits are used to subtract the transmit signal from the receive signal in a full duplex communication system. Since the hybrid circuit and the main line driver are exposed to different loads, accurate subtraction is difficult to achieve. A frequency dependent network is used to match the loading seen by the driver and the hybrid. The compensation network can be based on active and/or passive components.
摘要翻译：提供混合频率补偿。混合电路用于在全双工通信系统中从接收信号中减去发送信号。由于混合电路和主线驱动器暴露于不同的负载，因此难以实现精确的减法。使用频率相关网络来匹配驾驶员和混合动力车辆所看到的负载。补偿网络可以基于主动和/或无源组件。

38. 发明授权

US08107581B2 Method for frequency compensation in timing recovery 失效
标题翻译：定时恢复频率补偿方法
公开(公告)号：US08107581B2
公开(公告)日：2012-01-31
申请号：US12006831
申请日：2008-01-03
申请人： James M. Little , Hiroshi Takatori
发明人： James M. Little , Hiroshi Takatori
IPC分类号： H03D3/24
CPC分类号： H04L47/6245 , G06F1/10 , H03L7/00 , H04B3/32 , H04J3/0697 , H04L25/0278 , H04L43/16 , H04L47/25 , H04L47/521 , H04L47/6215 , H04L47/722
摘要： A method of digitally controlling a timing recovery loop to control jitter and reduce word-length in a recovered clock is provided. A timing error detector provides an output identifying the error sign. First and second randomizing digital attenuators provide first and second estimates of the phase error in a timing signal. A controller receives the first estimate and provides a signal to an NCO. An output from the NCO provides feedback to the error detector to complete a first order feedback loop, providing a first estimate phase error compensation. An integrator receives the second estimate and provides an output estimate for frequency offset of the timing signal that is received by the controller and the sign and magnitude of the integrated phase error are calibrated to provide a frequency offset. The controller determines a number of additional updates to the NCO required to minimize jitter and reduce word-length.
摘要翻译：提供了一种数字控制定时恢复环路以控制抖动并减少恢复时钟中的字长的方法。定时误差检测器提供识别错误符号的输出。第一和第二随机数字衰减器提供定时信号中的相位误差的第一和第二估计。控制器接收第一估计并向NCO提供信号。来自NCO的输出向误差检测器提供反馈以完成一阶反馈回路，提供第一估计相位误差补偿。积分器接收第二估计并提供对由控制器接收的定时信号的频率偏移的输出估计，并且对积分相位误差的符号和幅度进行校准以提供频率偏移。控制器确定了为了最小化抖动和减少字长所需的NCO的额外更新数量。

39. 发明授权

US07999708B2 Analog correction of a phase-mismatch in high-sample rate time-interleaved analog-to-digital converters 有权
标题翻译：高采样率时间交织模数转换器中的相位失配的模拟校正
公开(公告)号：US07999708B2
公开(公告)日：2011-08-16
申请号：US12631531
申请日：2009-12-04
申请人： Kenneth C. Dyer
发明人： Kenneth C. Dyer
IPC分类号： H03M1/06
CPC分类号： H04L47/6245 , G06F1/10 , H03L7/00 , H04B3/32 , H04J3/0697 , H04L25/0278 , H04L43/16 , H04L47/25 , H04L47/521 , H04L47/6215 , H04L47/722
摘要： A method of phase mismatch correction in high-sample rate time-interleaved analog-to-digital converters (ADC) is provided. An ADC parallel array has an output signal that is processed by a phase-mismatch detector. The detector drives a clock generator control circuit for the ADC array. The clock generator includes a common mode logic (CML) buffer, a CMOS, a non-overlapping generator, a DAC and a decimating low-pass filter. The CML receives a reference clock signal providing source line control (SLC) to the CMOS, the CMOS provides SLC to the DAC that is controlled by the filter which receives a digital control signal from the phase mismatch detector. The DAC provides a corrected timing input to the CMOS that provides the corrected timing signal to the non-overlap generator, where a delay in the clock path is modified and the signal path is unaltered.
摘要翻译：提供了高采样率时间交织模数转换器（ADC）中的相位失配校正方法。 ADC并行阵列具有由相位失配检测器处理的输出信号。检测器驱动ADC阵列的时钟发生器控制电路。时钟发生器包括共模逻辑（CML）缓冲器，CMOS，非重叠发生器，DAC和抽取低通滤波器。 CML接收提供CMOS线路线控制（SLC）的参考时钟信号，CMOS为DAC提供SLC，该滤波器由接收来自相位失配检测器的数字控制信号的滤波器控制。 DAC为CMOS提供校正的定时输入，其向校正的发生器提供校正的定时信号，其中时钟路径中的延迟被修改并且信号路径不变。

40. 发明申请

US20110141875A1 COMBINED ECHO AND CROSSTALK CANCELLATION 有权
标题翻译：组合的ECHO和CROSSTALK CANCELLATION
公开(公告)号：US20110141875A1
公开(公告)日：2011-06-16
申请号：US13025942
申请日：2011-02-11
申请人： James M. Little , Marwan Hassoun , David Tetzlaff , Chang-Chi Liu
发明人： James M. Little , Marwan Hassoun , David Tetzlaff , Chang-Chi Liu
IPC分类号： H04J4/00
CPC分类号： H04L47/6245 , G06F1/10 , H03L7/00 , H04B3/32 , H04J3/0697 , H04L25/0278 , H04L43/16 , H04L47/25 , H04L47/521 , H04L47/6215 , H04L47/722
摘要： Combined echo and crosstalk cancellation is provided. Frequency domain adaptive filters are used to remove or reduce the effects of echo and crosstalk for a multi-channel and full-duplex communications system. Data from each transmit channel is buffered and converted to the frequency domain. The frequency domain data is multiplied by crosstalk coefficients to obtain a frequency domain correction signal for each channel. Adaptation of the crosstalk coefficients is based on correlations between the error signals and the data from each of the transmit channels. A single frequency domain transform engine, such as a Fast Fourier Transform engine, is employed for all calculations to save power and area.
摘要翻译：提供了组合回波和串扰消除。频域自适应滤波器用于消除或减少多通道和全双工通信系统的回波和串扰的影响。来自每个发射信道的数据被缓冲并转换到频域。频域数据乘以串扰系数，以获得每个通道的频域校正信号。串扰系数的适应基于误差信号与来自每个发射信道的数据之间的相关性。采用单频域变换引擎，如快速傅里叶变换引擎，用于所有计算，以节省功率和面积。

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