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31. 发明申请

US20160049296A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成半导体器件的方法
公开(公告)号：US20160049296A1
公开(公告)日：2016-02-18
申请号：US14920379
申请日：2015-10-22
申请人： Infineon Technologies AG
发明人： Hans-Joachim Schulze , Markus Zundel , Anton Mauder , Andreas Meiser , Franz Hirler , Hans Weber
IPC分类号： H01L21/02 , H01L29/66 , H01L21/265
CPC分类号： H01L21/02258 , H01L21/02164 , H01L21/02233 , H01L21/02238 , H01L21/02299 , H01L21/02345 , H01L21/26506 , H01L21/26513 , H01L21/32105 , H01L29/66325 , H01L29/66477
摘要： A method for forming a semiconductor device includes carrying out an anodic oxidation of a surface region of a semiconductor substrate to form an oxide layer at a surface of the semiconductor substrate by generating an attracting electrical field between the semiconductor substrate and an external electrode within an electrolyte to attract oxidizing ions of the electrolyte, causing an oxidation of the surface region of the semiconductor substrate. Further, the method includes reducing the number of remaining oxidizing ions within the oxide layer, while the semiconductor substrate is within an electrolyte.
摘要翻译：一种形成半导体器件的方法包括：通过在半导体衬底和半导体衬底内的外部电极之间产生吸引电场，在半导体衬底的表面上进行半导体衬底的表面区域的阳极氧化以形成氧化物层以吸引电解质的氧化离子，引起半导体衬底的表面区域的氧化。此外，该方法包括减少氧化物层内剩余氧化离子的数量，同时半导体衬底在电解质内。

32. 发明授权

US09245811B2 Method for postdoping a semiconductor wafer 有权
标题翻译：后掺杂半导体晶片的方法
公开(公告)号：US09245811B2
公开(公告)日：2016-01-26
申请号：US14454741
申请日：2014-08-08
申请人： Infineon Technologies AG
发明人： Reinhard Ploss , Helmut Oefner , Hans-Joachim Schulze
IPC分类号： H01L21/48 , H01L21/66 , H01L21/265 , H01L21/324 , H01L21/261 , H01L21/263 , H01L29/36 , H01L29/66
CPC分类号： H01L22/20 , H01L21/261 , H01L21/263 , H01L21/265 , H01L21/26513 , H01L21/324 , H01L22/12 , H01L22/14 , H01L29/32 , H01L29/36 , H01L29/66325 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/74 , H01L29/7813 , H01L29/8611 , H01L29/872
摘要： A method for treating a semiconductor wafer having a basic doping is disclosed. The method includes determining a doping concentration of the basic doping, and adapting the basic doping of the semiconductor wafer by postdoping. The postdoping includes at least one of the following methods: a proton implantation and a subsequent thermal process for producing hydrogen induced donors, and a neutron irradiation. In this case, at least one of the following parameters is dependent on the determined doping concentration of the basic doping: an implantation dose of the proton implantation, a temperature of the thermal process, and an irradiation dose of the neutron irradiation.
摘要翻译：公开了一种用于处理具有基本掺杂的半导体晶片的方法。该方法包括确定基本掺杂的掺杂浓度，以及通过后掺杂来适应半导体晶片的基本掺杂。后掺杂包括以下方法中的至少一种：用于产生氢诱导的供体的质子注入和随后的热处理以及中子照射。在这种情况下，以下参数中的至少一个取决于所确定的碱性掺杂的掺杂浓度：质子注入的注入剂量，热处理的温度和中子照射的照射剂量。

33. 发明申请

US20160005836A1 HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
标题翻译：异相双极晶体管
公开(公告)号：US20160005836A1
公开(公告)日：2016-01-07
申请号：US14853719
申请日：2015-09-14
申请人： STMicroelectronics S.A.
发明人： Pascal CHEVALIER , Didier CELI , Jean-Pierre BLANC , Alain CHANTRE
IPC分类号： H01L29/66 , H01L27/06
CPC分类号： H01L29/66242 , H01L21/8249 , H01L27/0623 , H01L29/66325 , H01L29/737 , H01L29/7378
摘要： The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.
摘要翻译：本公开涉及一种方法，其包括在第一和第二隔离沟槽之间的第一区域中暴露硅衬底的表面，在第一区域中蚀刻硅衬底以在第一和第二隔离沟槽之间形成凹陷，以及形成通过在凹部中包含SiGe的膜的选择性外延生长，异质结双极晶体管的基极。

34. 发明授权

US09171944B2 Self-adaptive composite tunneling field effect transistor and method for fabricating the same 有权
标题翻译：自适应复合隧道场效应晶体管及其制造方法
公开(公告)号：US09171944B2
公开(公告)日：2015-10-27
申请号：US14117007
申请日：2013-04-27
申请人： Peking University
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Yingxin Qiu , Yangyuan Wang
IPC分类号： H01L29/06 , H01L29/66 , H01L29/739 , H01L29/08 , H01L21/265 , H01L21/266 , H01L21/324 , H01L21/28
CPC分类号： H01L29/66977 , H01L21/26513 , H01L21/266 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/0649 , H01L29/0847 , H01L29/66325 , H01L29/7391
摘要： The present invention provides a tunneling field effect transistor and a method for fabricating the same which refer to a field effect transistor logic device and circuit in a CMOS ultra-large integrated circuit (ULSI). The inventive concept of the invention lies in that, in a case of an N-type transistor, a side portion of a doped source region adjacent to an edge of the control gate is further implanted with P+ impurities on a basis of the doped source region being initially doped N− impurities, so that the initial N− impurities in the implanted portion are completely compensated by the P+ impurities, and in a case of a P-type transistor, a side portion of the doped source region adjacent to an edge of the control gate is implanted with N+ impurities on a basis of the doped source region being initially doped P− impurities, so that the initial P− impurities in the implanted portion are completely compensated by the N+ impurities. In the transistor, the source region is implanted twice with different doping concentrations, such that a large current characteristic of the MOSFET can be effectively combined to increase an on-state current of the transistor, and also, the threshold adjustment for the MOSFET portion and the TFET portion of the transistor can be achieved in a self-adaptive way.
摘要翻译：本发明提供一种隧道场效应晶体管及其制造方法，其涉及CMOS超大型集成电路（ULSI）中的场效应晶体管逻辑器件和电路。本发明的发明构思在于，在N型晶体管的情况下，与掺杂源极区相邻的掺杂源极区的侧面部分在掺杂源极区域的基础上进一步注入P +杂质初始掺杂的N杂质，使得注入部分中的初始N杂质被P +杂质完全补偿，并且在P型晶体管的情况下，掺杂源极区的与边缘的边缘相邻的侧部基于掺杂源区域，初始掺杂P杂质，控制栅极注入N +杂质，使得注入部分中的初始P-杂质被N +杂质完全补偿。在晶体管中，源区域以不同的掺杂浓度注入两次，使得可以有效地组合MOSFET的大电流特性以增加晶体管的导通电流，以及MOSFET部分的阈值调整和可以以自适应的方式实现晶体管的TFET部分。

35. 发明授权

US09117872B2 Semiconductor device and method for manufacturing the semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09117872B2
公开(公告)日：2015-08-25
申请号：US14037549
申请日：2013-09-26
申请人： Sanken Electric Co., Ltd.
发明人： Katsuyuki Torii
IPC分类号： H01L29/66 , H01L29/739 , H01L29/10
CPC分类号： H01L29/7395 , H01L29/1095 , H01L29/66325 , H01L29/66348 , H01L29/7393 , H01L29/7397
摘要： A semiconductor device includes a p-type collector region, a drift region arranged on the collector region, a base region arranged on the drift region, an emitter region arranged on the base region, a gate oxide film arranged on the bottom surface and side surface of a trench which penetrates the emitter region and the base region, and a gate electrode embedded in the inside of the trench so as to be opposed to the base region while interposing the gate oxide film therebetween, wherein the position of the lower surface of the base region is shallower in the region brought into contact with the gate oxide film than in the region spaced apart from the gate oxide film.
摘要翻译：半导体器件包括p型集电极区域，布置在集电极区域上的漂移区域，布置在漂移区域上的基极区域，布置在基极区域上的发射极区域，设置在底表面上的栅氧化膜和侧表面穿过所述发射极区域和所述基极区域的沟槽，以及嵌入在所述沟槽内部的栅极电极，以与所述基极区域相对，同时在其间插入所述栅极氧化膜，其中所述栅极电极的下表面的位置在与栅极氧化膜分离的区域中，与栅极氧化膜接触的区域的基极区域较浅。

36. 发明申请

US20150236139A1 SELF-ADAPTIVE COMPOSITE TUNNELING FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：自适应复合隧道场效应晶体管及其制造方法
公开(公告)号：US20150236139A1
公开(公告)日：2015-08-20
申请号：US14117007
申请日：2013-04-27
申请人： Peking University
发明人： Ru Huang , Qianqian Huang , Zhan Zhan , Yingxin Qiu , Yangyuan Wang
IPC分类号： H01L29/66 , H01L29/08 , H01L21/28 , H01L21/265 , H01L21/266 , H01L21/324 , H01L29/739 , H01L29/06
CPC分类号： H01L29/66977 , H01L21/26513 , H01L21/266 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/0649 , H01L29/0847 , H01L29/66325 , H01L29/7391
摘要： The present invention provides a tunneling field effect transistor and a method for fabricating the same which refer to a field effect transistor logic device and circuit in a CMOS ultra-large integrated circuit (ULSI). The inventive concept of the invention lies in that, in a case of an N-type transistor, a side portion of a doped source region adjacent to an edge of the control gate is further implanted with P+ impurities on a basis of the doped source region being initially doped N− impurities, so that the initial N− impurities in the implanted portion are completely compensated by the P+ impurities, and in a case of a P-type transistor, a side portion of the doped source region adjacent to an edge of the control gate is implanted with N+ impurities on a basis of the doped source region being initially doped P− impurities, so that the initial P− impurities in the implanted portion are completely compensated by the N+ impurities. In the transistor, the source region is implanted twice with different doping concentrations, such that a large current characteristic of the MOSFET can be effectively combined to increase an on-state current of the transistor, and also, the threshold adjustment for the MOSFET portion and the TFET portion of the transistor can be achieved in a self-adaptive way.
摘要翻译：本发明提供一种隧道场效应晶体管及其制造方法，其涉及CMOS超大型集成电路（ULSI）中的场效应晶体管逻辑器件和电路。本发明的发明构思在于，在N型晶体管的情况下，与掺杂源极区相邻的掺杂源极区的侧面部分在掺杂源极区域的基础上进一步注入P +杂质初始掺杂的N杂质，使得注入部分中的初始N杂质被P +杂质完全补偿，并且在P型晶体管的情况下，掺杂源极区的与边缘的边缘相邻的侧部基于掺杂源区域，初始掺杂P杂质，控制栅极注入N +杂质，使得注入部分中的初始P-杂质被N +杂质完全补偿。在晶体管中，源区域以不同的掺杂浓度注入两次，使得可以有效地组合MOSFET的大电流特性以增加晶体管的导通电流，以及MOSFET部分的阈值调整和可以以自适应的方式实现晶体管的TFET部分。

37. 发明授权

US09111898B2 Multiple layer substrate 有权
标题翻译：多层基板
公开(公告)号：US09111898B2
公开(公告)日：2015-08-18
申请号：US13770438
申请日：2013-02-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Long-Shih Lin , Fu-Hsiung Yang , Kun-Ming Huang , Ming-Yi Lin , Paul Chu
IPC分类号： B32B9/04 , B32B13/04 , H01L21/02 , H01L29/36 , H01L29/66 , H01L29/739 , H01L29/06 , H01L21/762
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/02488 , H01L21/0257 , H01L21/02587 , H01L21/76262 , H01L29/0619 , H01L29/36 , H01L29/66325 , H01L29/7394
摘要： A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration.
摘要翻译：用于集成电路的衬底包括具有原始载流子浓度的器件晶片和设置在器件晶片上的外延层。外延层具有第一载流子浓度。第一载流子浓度高于原载流子浓度。

38. 发明授权

US09076837B2 Lateral insulated gate bipolar transistor structure with low parasitic BJT gain and stable threshold voltage 有权
标题翻译：具有低寄生BJT增益和稳定阈值电压的横向绝缘栅双极晶体管结构
公开(公告)号：US09076837B2
公开(公告)日：2015-07-07
申请号：US13543662
申请日：2012-07-06
申请人： Long-Shih Lin , Kun-Ming Huang , Ming-Yi Lin
发明人： Long-Shih Lin , Kun-Ming Huang , Ming-Yi Lin
IPC分类号： H01L29/49 , H01L29/739 , H01L29/66 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423
CPC分类号： H01L29/66325 , H01L21/8222 , H01L29/0634 , H01L29/0696 , H01L29/0808 , H01L29/0847 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/66931 , H01L29/7393 , H01L29/7394 , H01L29/7816 , H01L29/7824 , H01L29/7835
摘要： A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure.
摘要翻译：本公开提供了金属氧化物半导体横向扩散器件（HV LDMOS），特别是横向绝缘栅双极结型晶体管（LIGBT）及其制造方法。该器件包括具有漂移区的漂移区绝缘体（SOI）衬底，漂移区中的两个相对掺杂的阱区，漂移区和第二阱区中的两个绝缘结构，第二阱区，栅极结构和源极在第二阱区域中的第三阱区域中嵌入第二阱区域。第三阱区域设置在栅极结构和第二绝缘结构之间。

39. 发明申请

US20150155182A1 METHOD FOR REMOVING A POLYSILICON PROTECTION LAYER ON A BACK FACE OF AN IGBT HAVING A FIELD STOP STRUCTURE 有权
标题翻译：在具有现场停止结构的IGBT的背面上移除多晶硅保护层的方法
公开(公告)号：US20150155182A1
公开(公告)日：2015-06-04
申请号：US14411978
申请日：2013-07-25
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Qiang Rui , Shuo Zhang , Genyi Wang , Xiaoshe Deng
IPC分类号： H01L21/311 , H01L29/66
CPC分类号： H01L21/31116 , H01L21/32105 , H01L21/32137 , H01L29/66325 , H01L29/66333
摘要： Disclosed is a method for removing a polysilicon protection layer (12) on a back face of an IGBT having a field stop structure (10). The method comprises thermally oxidizing the polysilicon protection layer (12) on the back face of the IGBT until the oxidation is terminated on a gate oxide layer (11) located above the polysilicon protection layer (12) to form a silicon dioxide layer (13), and removing the formed silicon dioxide layer (13) and the gate oxide layer (11) by a dry etching process. The method for removing the protection layer is easier to control.
摘要翻译：公开了一种在具有场停止结构（10）的IGBT的背面上去除多晶硅保护层（12）的方法。该方法包括在IGBT的背面上热氧化多晶硅保护层（12），直到在位于多晶硅保护层（12）上方的栅极氧化物层（11）上终止氧化以形成二氧化硅层（13），并通过干式蚀刻工艺除去形成的二氧化硅层（13）和栅极氧化物层（11）。去除保护层的方法更容易控制。

40. 发明申请

US20150144990A1 POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20150144990A1
公开(公告)日：2015-05-28
申请号：US14273378
申请日：2014-05-08
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人： Jae Hoon PARK , In Hyuk SONG , Dong Soo SEO , Ji Yeon OH , Kee Ju UM
IPC分类号： H01L29/423 , H01L29/73 , H01L21/28 , H01L29/66
CPC分类号： H01L29/66325 , H01L29/42368 , H01L29/512 , H01L29/513 , H01L29/518 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A power semiconductor device may include a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type formed on an upper portion of the first semiconductor region, a third semiconductor region having a first conductivity type formed in an inner portion of an upper portion of the second semiconductor region, a trench gate formed to penetrate from the third semiconductor region to the first semiconductor region and including a first insulating layer formed on a surface thereof, and a second insulating layer formed in a lower portion of the trench gate.
摘要翻译：功率半导体器件可以包括具有第一导电类型的第一半导体区域，形成在第一半导体区域的上部上的具有第二导电类型的第二半导体区域，形成在内部的第一导电类型的第三半导体区域第二半导体区域的上部的沟槽栅极，形成为从第三半导体区域穿透到第一半导体区域并且包括形成在其表面上的第一绝缘层的沟槽栅极和形成在第二半导体区域的下部的第二绝缘层沟槽门

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