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31. 发明授权

US5362370A Method for the electrolytic removal of plastic mold flash or bleed from the metal surfaces of semiconductor devices or similar electronic components 失效
标题翻译：用于电解去除塑料模具的方法闪蒸或从半导体器件或类似电子部件的金属表面渗出
公开(公告)号：US5362370A
公开(公告)日：1994-11-08
申请号：US64665
申请日：1993-05-21
申请人： Henricus J. van der Heijden
发明人： Henricus J. van der Heijden
IPC分类号： C25F1/00 , C25F3/00 , H01L21/48 , H01L21/56 , H01L23/50
CPC分类号： H01L21/4864 , C25F1/00 , H01L2924/0002
摘要： Immersing semiconductor devices and similar electronic components in an aqueous solution of one or more organic solvents, conducting salts and a wetting agent and connecting the components to be cleaned to the negative pole of a source of direct current, of which the positive pole is connected to an anode in the same solution, and passing current through the solution raises the pH of the electrolyte film on the cathodic metal surface to a value whereby the organic solvent causes a softening of the plastic mold flash or bleed, sufficient to enable the hydrogen gas generated simultaneously on the cathode to remove the plastic mold flash or bleed from the metal surfaces.
摘要翻译：将半导体器件和类似的电子部件浸入一种或多种有机溶剂的水溶液中，导电盐和润湿剂，并将待清洁的组分连接到直流电源的负极，其中正极连接到同一溶液中的阳极和通过溶液的电流将阴极金属表面上的电解质膜的pH提高到一个值，由此有机溶剂引起塑料模具的软化或闪蒸，足以使氢气产生同时在阴极上移除塑料模具，闪光或从金属表面渗出。

32. 发明授权

US5332879A Method for removing trace metal contaminants from organic dielectrics 失效
标题翻译：从有机电介质中去除痕量金属污染物的方法
公开(公告)号：US5332879A
公开(公告)日：1994-07-26
申请号：US984605
申请日：1992-12-02
申请人： Gouri Radhakrishnan , Heinrich G. Muller
发明人： Gouri Radhakrishnan , Heinrich G. Muller
IPC分类号： B08B7/00 , B23K26/40 , H01L21/48 , B23K26/16
CPC分类号： H01L21/4864 , B08B7/0042 , B23K26/362 , B23K26/402 , B23K2203/30 , B23K2203/42
摘要： A technique is described for the removal of trace metal contaminants from organic dielectrics such as polyimide. Pulsed ultraviolet radiation is used to remove the contaminants from the dielectric, regardless of their chemical nature, by the process of ablation. The process allows prepatterned bulk metal features to be simultaneously exposed to the pulsed radiation and yet remain unaffected.
摘要翻译：描述了从有机电介质如聚酰亚胺中去除痕量金属污染物的技术。脉冲紫外线辐射用于通过消融过程从电介质中去除污染物，而不管其化学性质如何。该方法允许预制图案的体金属特征同时暴露于脉冲辐射，但仍保持不受影响。

33. 发明授权

US4954142A Method of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor 失效
标题翻译：电子部件基板的化学机械研磨方法及研磨用浆料的方法
公开(公告)号：US4954142A
公开(公告)日：1990-09-04
申请号：US285435
申请日：1989-03-07
申请人： Jeffrey W. Carr , Lawrence D. David , William L. Guthrie , Frank B. Kaufman , William J. Patrick , Kenneth P. Rodbell , Robert W. Pasco , Anton Nenadic
发明人： Jeffrey W. Carr , Lawrence D. David , William L. Guthrie , Frank B. Kaufman , William J. Patrick , Kenneth P. Rodbell , Robert W. Pasco , Anton Nenadic
IPC分类号： B24B37/00 , C09G1/02 , H01L21/304 , H01L21/306 , H01L21/48
CPC分类号： H01L21/4871 , C09G1/02 , H01L21/4864
摘要： Disclosed is a method of chem-mech polishing an electronic component substrate. The method includes the following steps;obtaining a substrate having at least two features thereon or therein which have a different etch rate with respect to a particular etchant; andcontacting the substrate with a polishing pad while contacting the substrate with a slurry containing the etchant wherein the slurry includes abrasive particles, a transition metal chelated salt and a solvent for the salt.The chem-mech polishing causes the at least two features to be substantially coplanar. Also disclosed is the chem-mech polishing slurry.
摘要翻译：公开了电子部件基板的化学研磨方法。该方法包括以下步骤：获得其上具有至少两个特征的衬底，其中相对于特定蚀刻剂具有不同的蚀刻速率; 以及使所述基板与抛光垫接触，同时使所述基板与含有所述蚀刻剂的浆料接触，其中所述浆料包括磨料颗粒，过渡金属螯合盐和所述盐的溶剂。化学铣削使得至少两个特征基本上共面。还公开了化学研磨浆料。

34. 发明授权

US4914813A Refurbishing of prior used laminated ceramic packages 失效
标题翻译：翻新现有的层压陶瓷包装
公开(公告)号：US4914813A
公开(公告)日：1990-04-10
申请号：US276238
申请日：1988-11-25
申请人： Francis W. Layher , Napoleon Fulinara
发明人： Francis W. Layher , Napoleon Fulinara
IPC分类号： H01L21/48
CPC分类号： H01L21/4864 , Y10T29/49149 , Y10T29/49721 , Y10T29/49726
摘要： The invention is directed to a process for refurbishing of prior used laminated ceramic packages with the example shown as a pin grid array ceramic package which includes a ceramic substrate with a central opening or cavity, a plurality of conductors are embedded therein in one or more layers which have electrical condtinuity from the outer edge thereof to the central opening (this continuity path may extend through one or more layers) and to an equal plurality of conductive pads on the surface of the substrate. The bottom surface of the cavity may be enclosed by a metallic heat sink cover, an electronic chip (die) is adhered by silver glass or other adhering substance to the bottom surface of the cavity and electrically connected via small diameter conductors to the ends of the plurality of embedded conductors adjacent to the central opening, a plurality of pins are physically and conductively attached to each of the conductive pad on the surface of the substrate and a cover attached over the chip for covering the electronic chip and conductors. In effect the laminated ceramic packages assembled as hereinbefore mentioned are precision reverse manufactured or stripped down by specific steps to a bare ceramic substrate and rebuilt to its original configuration for reuse.
摘要翻译：本发明涉及一种用于翻新现有使用的层压陶瓷封装的方法，其中所示的示例为引脚格栅阵列陶瓷封装，其包括具有中心开口或空腔的陶瓷基板，多个导体嵌入其中一个或多个层其从其外边缘到中心开口具有电连续性（该连续路径可以延伸穿过一个或多个层）以及衬底表面上的等量的多个导电焊盘。空腔的底面可以由金属散热器盖封闭，电子芯片（模具）通过银玻璃或其他粘附物质粘附到空腔的底表面，并通过小直径导体电连接到与中心开口相邻的多个嵌入式导体，多个引脚物理地和导电地连接到基板的表面上的每个导电焊盘，以及附接在芯片上的覆盖电子芯片和导体的盖。实际上，如上所述组装的层压陶瓷封装是通过特定步骤精确地反向制造或剥离到裸陶瓷衬底，并重建成其原始构型以供重复使用。

35. 发明授权

US4379218A Fluxless ion beam soldering process 失效
标题翻译：无焊离子束焊接工艺
公开(公告)号：US4379218A
公开(公告)日：1983-04-05
申请号：US278964
申请日：1981-06-30
申请人： Kurt R. Grebe , James M. E. Harper
发明人： Kurt R. Grebe , James M. E. Harper
IPC分类号： H05K3/34 , B23K1/005 , B23K1/20 , B23K17/00 , C23G5/00 , H01L21/48 , H01L21/52 , H01L21/60 , B23K15/00
CPC分类号： H01L24/81 , B23K1/005 , B23K1/206 , B23K17/00 , C23G5/00 , H01L21/4864 , B23K2201/40 , H01L2224/75 , H01L2224/75102 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/15787 , H05K3/3489
摘要： A method for fluxlessly joining members having relatively low melting materials is provided. The members to be joined are exposed to ion beam radiation of sufficient intensity and a time sufficient to cause cleaning of the low melting materials after cooling. The members are then placed into juxtaposition with each other and again exposed to ion beam radiation of an intensity and for a time sufficient to cause reflow of the low melting materials which upon cooling joins said members.
摘要翻译：提供一种无熔接合具有较低熔点的材料的方法。要连接的构件暴露于足够强度的离子束辐射和足以在冷却后对低熔点材料进行清洁的时间。然后将构件彼此并置放置并再次暴露于强度的离子束辐射，并且足够的时间引起在冷却结合所述构件时低熔点材料的回流。

36. 发明授权

US12051653B2 Reconstituted substrate for radio frequency applications 有权
公开(公告)号：US12051653B2
公开(公告)日：2024-07-30
申请号：US17872731
申请日：2022-07-25
申请人： Applied Materials, Inc.
发明人： Guan Huei See , Ramesh Chidambaram
IPC分类号： H01L23/538 , H01L21/48 , H01L21/50 , H01L21/768 , H01L23/13 , H01L23/14 , H01L23/498 , H01L23/66 , H01L25/065 , H01L25/10 , H01L27/06 , H01Q1/22 , H01Q1/24 , H05K1/02 , H01L21/60
CPC分类号： H01L23/5389 , H01L21/486 , H01L21/4864 , H01L21/50 , H01L21/76802 , H01L23/13 , H01L23/147 , H01L23/49827 , H01L23/49838 , H01L23/49866 , H01L23/49894 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L23/66 , H01L25/0657 , H01L25/105 , H01L27/0688 , H01Q1/2283 , H01Q1/243 , H05K1/0243 , H01L2021/60007 , H01L2225/1035 , H01L2225/107
摘要： The present disclosure relates to methods and apparatus for forming thin-form-factor reconstituted substrates and semiconductor device packages for radio frequency applications. The substrate and package structures described herein may be utilized in high-density 2D and 3D integrated devices for 4G, 5G, 6G, and other wireless network systems. In one embodiment, a silicon substrate is structured by laser ablation to include cavities for placement of semiconductor dies and vias for deposition of conductive interconnections. Additionally, one or more cavities are structured to be filled or occupied with a flowable dielectric material. Integration of one or more radio frequency components adjacent the dielectric-filled cavities enables improved performance of the radio frequency elements with reduced signal loss caused by the silicon substrate.

37. 发明公开

US20240237221A9 METHOD FOR MANUFACTURING WIRING SUBSTRATE 审中-公开
公开(公告)号：US20240237221A9
公开(公告)日：2024-07-11
申请号：US18489921
申请日：2023-10-19
申请人： IBIDEN CO., LTD.
发明人： Shogo FUKUI , Ryo ANDO , Keisuke SHIMIZU
IPC分类号： H05K1/18 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/498 , H05K3/00
CPC分类号： H05K1/186 , H01L21/4857 , H01L21/4864 , H01L21/56 , H01L23/49822 , H01L24/19 , H01L24/20 , H05K3/0035 , H05K3/0055 , H01L25/0652
摘要： A method for manufacturing a wiring substrate includes forming conductor pads on a surface of an insulating layer, positioning, on or in the insulating layer, an electronic component having electrode pads, forming a second insulating layer covering the surface of the insulating layer, conductor pads and electronic component, forming first via holes exposing the conductor pads, applying a first desmear treatment to the second insulating layer such that residues are removed from the first via holes, forming second via holes in the second insulating layer after the first desmear treatment such that the second via holes expose the electrode pads of the electronic component positioned on or in the insulating layer, applying a second desmear treatment to the second insulating layer such that residues are removed from the second via holes, forming first via conductors in the first via holes, and forming second via conductors in the second via holes.

38. 发明公开

US20230420353A1 ASYMMETRICAL DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES 审中-公开
公开(公告)号：US20230420353A1
公开(公告)日：2023-12-28
申请号：US17848053
申请日：2022-06-23
申请人： Intel Corporation
发明人： Suddhasattwa Nad , Yi Yang , Jason Steill , Jieying Kong
IPC分类号： H01L23/498 , H01L21/48
CPC分类号： H01L23/49838 , H01L23/49822 , H01L23/49811 , H01L23/49894 , H01L21/4857 , H01L21/486 , H01L21/4864 , H01L2924/35121 , H01L24/16
摘要： An electronic device package comprises a substrate with a first side and a second side opposite the first side; a first conductive feature on the first side and having a first surface; a first dielectric material in contact with the first surface, wherein the first dielectric material has a first composition comprising silicon and nitrogen; a second conductive feature on the second side of the substrate and having a second surface; and a second dielectric material in contact with the second surface, wherein the second dielectric material has a second composition different than the first composition, and wherein a surface roughness of the second surface is greater than a surface roughness of the first surface.

39. 发明授权

US11789366B2 Method for removing resist layer, and method of manufacturing semiconductor 有权
公开(公告)号：US11789366B2
公开(公告)日：2023-10-17
申请号：US17829366
申请日：2022-06-01
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hung-Jui Kuo , Hui-Jung Tsai , Tai-Min Chang
IPC分类号： G03F7/42 , H01L23/538 , H01L23/00 , H01L21/683 , H01L21/48 , H01L21/56 , H01L23/31
CPC分类号： G03F7/426 , H01L21/4853 , H01L21/4857 , H01L21/4864 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/5383 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L2221/68372 , H01L2224/214
摘要： A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.

40. 发明授权

US10867959B2 Integrated circuit packaging method and integrated packaged circuit 有权
公开(公告)号：US10867959B2
公开(公告)日：2020-12-15
申请号：US16464880
申请日：2016-11-30
申请人： Shenzhen Xiuyuan Electronic Technology Co., Ltd.
发明人： Chuan Hu , Junjun Liu , Yuejin Guo , Edward Rudolph Prack
IPC分类号： H01L23/00 , H01L21/48 , H01L23/498 , H01L23/12 , H05K1/00 , H01L21/56 , H01L23/31 , H01L23/538 , H01L25/065
CPC分类号： H01L24/83 , H01L21/486 , H01L21/4853 , H01L21/4864 , H01L21/4867 , H01L21/56 , H01L23/12 , H01L23/3128 , H01L23/4985 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L23/5387 , H01L24/32 , H01L25/0655 , H05K1/00 , H01L24/08 , H01L2224/08235 , H01L2224/3223 , H01L2224/32235 , H01L2224/838 , H01L2224/83013 , H01L2224/83031 , H01L2224/83039 , H01L2224/8385
摘要： An integrated circuit packaging method, including: a top surface of a substrate, a bottom surface of the substrate, or the interior of the substrate is provided with circuit layers, and the circuit layers are provided with circuit pins; a component element is mounted on the substrate, and a surface of the component element facing the substrate is provided with component pins; connection through holes are formed on the substrate, the connection through holes are made to abut on the circuit pins, and a first opening of the connection through holes is abutted on the component pins; conductive layers are fabricated inside of the connection through holes by means of a second opening of the connection through holes, and the conductive layers electrically connect the component pins with the circuit pins.

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