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31. 发明申请

US20030008516A1 Method of reinforcing a low dielectric constant material layer against damage caused by a photoresist stripper 审中-公开
标题翻译：加强低介电常数材料层以防止由光致抗蚀剂剥离剂引起的损伤的方法
公开(公告)号：US20030008516A1
公开(公告)日：2003-01-09
申请号：US09681985
申请日：2001-07-03
发明人： Ting-Chang Chang , Po-Tsun Liu , Yi-Shien Mor
IPC分类号： H01L021/302 , H01L021/461
CPC分类号： H01L21/76826 , H01L21/02134 , H01L21/02137 , H01L21/0234 , H01L21/31058 , H01L21/31138 , H01L21/3122 , H01L21/3124 , H01L21/76802 , H01L21/76829 , H01L21/76831
摘要： A low dielectric constant (low k) material layer is positioned on a semiconductor wafer. A first hydrogen-containing plasma treatment is performed to reinforce a surface of the low k material layer against corrosion caused by a photoresist stripper. A photoresist layer, having an opening in the photoresist layer to expose portions of the low k material layer, is then coated on the low k material layer. By dry etching the low k material layer through the opening, a pattern in the photoresist layer is transferred to the low k material layer. An ashing process with an oxygen plasma supply is then performed to ash the photoresist layer. Finally, the semiconductor wafer is dipped in a wet stripper to completely remove the photoresist layer.
摘要翻译：低介电常数（低k）材料层位于半导体晶片上。执行第一含氢等离子体处理以加强低k材料层的表面以抵抗由光致抗蚀剂剥离剂引起的腐蚀。然后将具有在光致抗蚀剂层中具有露出低k材料层的部分的开口的光致抗蚀剂层涂覆在低k材料层上。通过通过开口干燥蚀刻低k材料层，光致抗蚀剂层中的图案被转移到低k材料层。然后进行具有氧等离子体供应的灰化处理以使光致抗蚀剂层灰化。最后，将半导体晶片浸入湿式剥离器中以完全除去光致抗蚀剂层。

32. 发明申请

US20020106891A1 Method of fabricating semiconductor devices having low dielectric interlayer insulation layer 失效
标题翻译：制造具有低介电层间绝缘层的半导体器件的方法
公开(公告)号：US20020106891A1
公开(公告)日：2002-08-08
申请号：US09994508
申请日：2001-11-27
申请人： Samsung Electronics Co., Ltd.
发明人： Jae-Hak Kim , Hong-Jae Shin , Soo-Geun Lee , Kyoung-Woo Lee
IPC分类号： H01L021/4763 , H01L023/48 , H01L023/52 , H01L021/469
CPC分类号： H01L21/76826 , H01L21/02126 , H01L21/02137 , H01L21/02211 , H01L21/02274 , H01L21/02282 , H01L21/0234 , H01L21/02362 , H01L21/3144 , H01L21/31633 , H01L21/76801 , H01L21/76802 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device having a low dielectric constant is disclosed. According to the method, a silicon oxycarbide layer is formed, treated with plasma, and patterned. The silicon oxycarbide layer is formed by a coating method or a CVD method such as a PECVD method. Treating the silicon oxycarbide layer with plasma is performed by supplying at least one gas selected from a group of He, H2, N2O, NH3, N2, O2 and Ar. It is desirable that plasma be applied at the silicon oxycarbide layer in a PECVD device by an in situ method after forming the silicon oxycarbide layer. In a case in which a capping layer is further stacked and patterned, it is desirable to treat with H2-plasma. Even in a case in which an interlayer insulation is formed of the silicon oxycarbide layer and a coating layer of an organic polymer group for a dual damascene process, it is desirable to perform the plasma treatment before forming the coating layer.
摘要翻译：公开了一种制造具有低介电常数的半导体器件的方法。根据该方法，形成碳氧化硅层，用等离子体处理并图案化。碳硅氧化物层通过涂布法或CVD法如PECVD法形成。通过供给选自He，H 2，N 2 O，NH 3，N 2，O 2和Ar的至少一种气体来进行用等离子体处理碳氧化硅层。希望在形成硅碳化硅层之后，通过原位法将等离子体施加在PECVD器件中的碳氧化硅层。在封盖层进一步堆叠和图案化的情况下，期望用H 2等离子体处理。即使在由硅碳化硅层和双镶嵌工艺的有机聚合物基团的涂层形成层间绝缘的情况下，期望在形成涂层之前进行等离子体处理。

33. 发明授权

US06258715B1 Process for low-k dielectric with dummy plugs 有权
标题翻译：具有虚拟插头的低k电介质的工艺
公开(公告)号：US06258715B1
公开(公告)日：2001-07-10
申请号：US09228125
申请日：1999-01-11
申请人： Chen-Hua Yu , Shwangming Jeng
发明人： Chen-Hua Yu , Shwangming Jeng
IPC分类号： H01L214763
CPC分类号： H01L23/564 , H01L21/02134 , H01L21/02137 , H01L21/3124 , H01L21/76801 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Low dielectric inter-metal dielectric (IMD) layers made of hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ) spin-on-glass do not have good thermal conductivity as compared to regular oxides, in addition the adhesion of HSQ or MSQ is worse than that of oxide to oxide layers Methods are disclosed and illustrated to improve the heat transfer by providing metal dummy plugs under and/or around bonding pads or between metallization layers. The arrangement and numbers of dummy plugs depends on the heat to be transferred and varies with the application. Good thermal conductivity is of particular importance because the effects of high local temperature around bonding pads during chip bonding results in thermal stress and delamination of the IMD layers. The use of bonding pads provides other benefits as well.
摘要翻译：与常规氧化物相比，氢倍半硅氧烷（HSQ）或甲基倍半硅氧烷（MSQ）旋涂玻璃制成的低介电金属间介质（IMD）层不具有良好的导热性，此外，HSQ或MSQ的粘附性更差比氧化物到氧化物层的方法公开和示出了通过在焊盘下方和/或周围在金属化层之间提供金属虚拟插头来改善热传递。虚拟插头的布置和数量取决于要传输的热量，并随应用而变化。良好的导热性是特别重要的，因为芯片接合期间接合焊盘周围的高局部温度的影响导致IMD层的热应力和分层。焊接垫的使用也提供了其他好处。

34. 发明授权

US06177360B1 Process for manufacture of integrated circuit device 失效
标题翻译：集成电路器件制造工艺
公开(公告)号：US06177360B1
公开(公告)日：2001-01-23
申请号：US08965384
申请日：1997-11-06
申请人： Kenneth Raymond Carter , Robert Frances Cook , Martha Alyne Harbison , Craig Jon Hawker , James Lupton Hedrick , Victor Yee-Way Lee , Eric Gerhard Liniger , Robert Dennis Miller , Willi Volksen , Do Yeung Yoon
发明人： Kenneth Raymond Carter , Robert Frances Cook , Martha Alyne Harbison , Craig Jon Hawker , James Lupton Hedrick , Victor Yee-Way Lee , Eric Gerhard Liniger , Robert Dennis Miller , Willi Volksen , Do Yeung Yoon
IPC分类号： H01L2131
CPC分类号： H01L21/02137 , H01L21/02282 , H01L21/3122 , H01L21/76801
摘要： The invention relates to a process for making an integrated circuit device comprising (i) a substrate, (ii) metallic circuit lines positioned on the substrate, and (iii) a dielectric material positioned on the circuit lines. The dielectric material comprises the condensation product of silsesquioxane in the presence of a photosensitive or thermally sensitive base generator.
摘要翻译：本发明涉及一种用于制造集成电路器件的方法，该集成电路器件包括（i）衬底，（ii）位于衬底上的金属电路线，以及（iii）位于电路线上的电介质材料。电介质材料包括在感光或热敏基底发生器存在下倍半硅氧烷的缩合产物。

35. 发明授权

US6143646A Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation 失效
标题翻译：双重嵌入式集成电路结构，具有选择性定位的低K电介质隔离和形成方法
公开(公告)号：US6143646A
公开(公告)日：2000-11-07
申请号：US868332
申请日：1997-06-03
申请人： Jeffrey Thomas Wetzel
发明人： Jeffrey Thomas Wetzel
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/02118 , H01L21/02137 , H01L21/31053 , H01L21/31695 , H01L21/76801 , H01L21/76807 , H01L21/76813 , H01L2221/1031 , H01L2924/0002
摘要： A method for forming a dual inlaid contact structure (damascene) begins by etching dual inlaid contact structures (32, 34, and 36). Masking layers (28) are (228) and the deposition of low-K dielectric material 26 is used to selectively form low-K regions (30) only in critical areas where low-K dielectric material is absolutely needed. Other portions of the wafer remain covered with conventional oxide (24) so that adverse impacts of low-K dielectric material is minimized. Conductive material (38, 40, and 42) is then formed to complete dual inlaid contact structures whereby low-K dielectric plugs (30) reduce cross talk and capacitance within the final structure.
摘要翻译：形成双镶嵌接触结构（镶嵌）的方法首先通过蚀刻双重镶嵌接触结构（32,34和36）开始。遮蔽层（28）是（228），并且低K电介质材料26的沉积用于仅在绝对需要低K介电材料的关键区域中选择性地形成低K区域（30）。晶片的其他部分保持用常规氧化物（24）覆盖，使得低K电介质材料的不利影响最小化。然后形成导电材料（38,40和42）以完成双重镶嵌接触结构，由此低K电介质塞（30）减少最终结构内的串扰和电容。

36. 发明授权

US5889330A Semiconductor device whose flattening resin film component has a controlled carbon atom content 失效
标题翻译：其平坦化树脂膜组分具有受控碳原子含量的半导体器件
公开(公告)号：US5889330A
公开(公告)日：1999-03-30
申请号：US987763
申请日：1997-12-09
申请人： Hiroyuki Nishimura , Hiroshi Adachi , Etsushi Adachi , Shigeyuki Yamamoto , Shintaro Minami , Shigeru Harada , Toru Tajima , Kimio Hagi
发明人： Hiroyuki Nishimura , Hiroshi Adachi , Etsushi Adachi , Shigeyuki Yamamoto , Shintaro Minami , Shigeru Harada , Toru Tajima , Kimio Hagi
IPC分类号： H01L21/312 , H01L21/768 , H01L23/532 , H01L29/41
CPC分类号： H01L21/02137 , H01L21/02282 , H01L21/02304 , H01L21/0234 , H01L21/02362 , H01L21/3122 , H01L21/76801 , H01L21/76826 , H01L23/5329 , H01L2924/0002
摘要： In a semiconductor device and a method of fabrication thereof, a resin film forms an interlayer film of the semiconductor device having a multilayer interconnection structure, and is formed by only one coating using coating liquid containing silicone ladder polymers represented by the chemical formula: (HO).sub.2 (R.sub.2 Si.sub.2 O.sub.3).sub.n H.sub.2. As a result, it is possible to improve long-term reliability of electric characteristics or the like, and simplify a process.
摘要翻译：在半导体器件及其制造方法中，树脂膜形成具有多层互连结构的半导体器件的中间膜，并且仅使用包含由以下化学式表示的硅树脂聚合物的涂布液形成一个涂层：（HO ）2（R2Si2O3）nH2。结果，可以提高电特性等的长期可靠性，并且简化工艺。

37. 发明授权

US09859129B2 Semiconductor device and manufacturing method of the same 有权
公开(公告)号：US09859129B2
公开(公告)日：2018-01-02
申请号：US15054142
申请日：2016-02-26
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ting-Huang Kuo , Chia-Pin Lo , Wei-Barn Chen , Chen-Chieh Chiang , Chii-Ming Wu , Chi-Cherng Jeng
IPC分类号： H01L29/167 , H01L29/51 , H01L29/78 , H01L21/3115 , H01L21/8238 , H01L21/3105 , H01L21/32 , H01L21/02 , H01L27/092
CPC分类号： H01L27/0922 , H01L21/02134 , H01L21/02137 , H01L21/3105 , H01L21/823821 , H01L27/0924
摘要： Semiconductor devices and manufacturing method of the same are disclosed. A semiconductor device includes a substrate, a p-type MOS transistor, an n-type MOS transistor and a cured flowable oxide layer. The substrate includes a first region and a second region. The p-type MOS transistor is in the first region. The n-type MOS transistor is in the second region. The cured flowable oxide layer covers the p-type MOS transistor and the n-type MOS transistor, wherein a first strain of the cured flowable oxide layer applying to the p-type MOS transistor is different from a second strain of the cured flowable oxide layer applying to the n-type MOS transistor, and the difference therebetween is greater than 0.002 Gpa.

38. 发明申请

US20170162496A1 TRENCH SILICIDE WITH SELF-ALIGNED CONTACT VIAS 有权
公开(公告)号：US20170162496A1
公开(公告)日：2017-06-08
申请号：US14962882
申请日：2015-12-08
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Michael A. Guillorn , Fei Liu , Adam M. Pyzyna
IPC分类号： H01L23/528 , H01L29/45 , H01L23/532 , H01L21/8234 , H01L23/522 , H01L21/768 , H01L21/02
CPC分类号： H01L23/528 , H01L21/02134 , H01L21/02137 , H01L21/76817 , H01L21/7684 , H01L21/7688 , H01L21/76886 , H01L21/76897 , H01L21/823418 , H01L21/823475 , H01L23/485 , H01L23/5226 , H01L23/5329 , H01L29/45
摘要： A modified trench metal-semiconductor alloy formation method involves depositing a layer of a printable dielectric or a sacrificial carbon material within a trench structure and over contact regions of a semiconductor device, and then selectively removing the printable dielectric or sacrificial carbon material to segment the trench and form plural contact vias. A metallization layer is formed within the contact vias and over the contact regions.

39. 发明授权

US08481669B2 Molding material comprising polysilsesquioxane compound, sealing material, and sealed optical element 有权
公开(公告)号：US08481669B2
公开(公告)日：2013-07-09
申请号：US12213283
申请日：2008-06-17
申请人： Mikihiro Kashio
发明人： Mikihiro Kashio
IPC分类号： C08G77/14
CPC分类号： C08G77/04 , C08G77/045 , C08G77/14 , C08G77/24 , C08L83/04 , H01L21/02137 , H01L21/3122 , Y10T428/31663
摘要： A molding material which can produce cured products with long-lasting excellent transparency and heat resistance, a sealing material in which the molding material is used, and a sealed optical element are provided. The molding material comprises a polysilsesquioxane compound with a ladder structure having a repeating unit of the following formula (I) in the molecule as a major component. wherein R1 represents a group shown by the formula AO—(CH2)r— (wherein A indicates a protective group for a hydroxyl group and r is an integer of 1 to 10), R2 represents a substituted or unsubstituted phenyl group, a substituted or unsubstituted (excluding substitution with OA in the above formula) alkyl group having 1 to 20 carbon atoms, or an alkenyl group having 2 to 20 carbon atoms, and l, m, and n individually represent 0 or an arbitrary integer, provided that l and n are not 0 at the same time.

40. 发明授权

US08372760B2 Method and system for using ion implantation for treating a low-k dielectric film 有权
标题翻译：用于处理低k电介质膜的离子注入的方法和系统
公开(公告)号：US08372760B2
公开(公告)日：2013-02-12
申请号：US10857935
申请日：2004-06-02
申请人： Kenneth Duerksen , David A. Vidusek
发明人： Kenneth Duerksen , David A. Vidusek
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/3105 , H01L21/02126 , H01L21/02134 , H01L21/02137 , H01L21/02203 , H01L21/02271 , H01L21/02282 , H01L21/02351 , H01L21/31058 , H01L21/31155 , H01L21/312 , H01L21/3121 , H01L21/67005
摘要： A system and method for forming a mechanically strengthened low-k dielectric film on a substrate includes using either spin-on-dielectric (SOD) techniques, or chemical vapor deposition (CVD) techniques to form a low-k dielectric film on the substrate. An upper surface of the low-k dielectric film is then treated in order to increase the film's mechanical strength, or reduce its dielectric constant.
摘要翻译：用于在衬底上形成机械强化的低k电介质膜的系统和方法包括使用旋涂电介质（SOD）技术或化学气相沉积（CVD）技术在衬底上形成低k电介质膜。然后处理低k电介质膜的上表面以增加膜的机械强度或降低其介电常数。

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