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31. 发明授权

US09311969B2 Systems and methods of storing data 有权
标题翻译：存储数据的系统和方法
公开(公告)号：US09311969B2
公开(公告)日：2016-04-12
申请号：US13329732
申请日：2011-12-19
申请人： Eran Sharon , Idan Alrod , Menahem Lasser
发明人： Eran Sharon , Idan Alrod , Menahem Lasser
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C7/10 , G06F11/10 , G11C11/56 , G11C16/04 , G11C16/10 , G11C29/00
CPC分类号： G11C7/1006 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C29/78 , G11C2211/5641
摘要： A method of writing data is performed in a data storage device with a controller and a memory. The memory includes latches and multiple storage elements and is operative to store a first number of bits in each storage element according to a first mapping of sequences of bits to states of the storage elements. The method includes loading data bits into the latches within the memory and generating manipulated data bits in the latches by manipulating designated data bits in the latches using one or more logical operations. The method also includes storing sets of the manipulated data bits to respective storage elements of the group of storage elements according to the first mapping. The designated data bits correspond to states of the respective storage elements according to a second mapping of sequences of bits to states. The second mapping is different than the first mapping.
摘要翻译：在具有控制器和存储器的数据存储装置中执行写入数据的方法。存储器包括锁存器和多个存储元件，并且可操作以根据比特序列到存储元件的状态的第一映射来在每个存储元件中存储第一数量的比特。该方法包括将数据位加载到存储器内的锁存器中，并通过使用一个或多个逻辑运算来操纵锁存器中的指定数据位来产生锁存器中的操纵数据位。该方法还包括根据第一映射将所操纵的数据位的组存储到该组存储元件的各个存储元件。指定的数据位根据比特序列到状态的第二映射对应于各个存储元件的状态。第二个映射与第一个映射不同。

32. 发明申请

US20160093403A1 METHOD AND APPARATUS FOR IN-SYSTEM REPAIR OF MEMORY IN BURST REFRESH 有权
标题翻译：用于系统修复烧录刷新存储器的方法和装置
公开(公告)号：US20160093403A1
公开(公告)日：2016-03-31
申请号：US14499161
申请日：2014-09-27
申请人： QUALCOMM Incorporated
发明人： Jung Pill KIM , Dexter Tamio CHUN , Deepti Vijayalakshmi SRIRAMAGIRI , Jungwon SUH
IPC分类号： G11C29/00 , G06F11/07 , G11C11/406 , G11C17/16 , G11C17/18
CPC分类号： G11C29/78 , G06F11/073 , G06F11/0751 , G06F11/0793 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/783 , G11C29/787
摘要： In a repair of a random access memory (RAM), an error information is received, a fail address of the RAM identified, and a one-time programming applied to a portion of the redundancy circuit while a content of the RAM is valid. Optionally, the RAM is a dynamic access RAM (DRAM), a refresh burst is applied to the DRAM, followed by a non-refresh interval, and the one-time programming is performed during the non-refresh interval.
摘要翻译：在随机存取存储器（RAM）的修复中，接收到错误信息，识别出的RAM的故障地址以及在RAM的内容有效时应用于冗余电路的一部分的一次性编程。可选地，RAM是动态访问RAM（DRAM），刷新突发被应用于DRAM，随后是非刷新间隔，并且在非刷新间隔期间执行一次性编程。

33. 发明申请

US20160086679A1 ELECTRONIC DEVICE 有权
标题翻译：电子设备
公开(公告)号：US20160086679A1
公开(公告)日：2016-03-24
申请号：US14603154
申请日：2015-01-22
申请人： SK hynix Inc.
发明人： Hyung-Dong LEE
IPC分类号： G11C29/00 , G11C17/18 , G11C13/00 , G11C17/16
CPC分类号： G11C29/78 , G11C17/16 , G11C17/18
摘要： An electronic device including a semiconductor memory unit that includes: a first access line coupled to a first memory cell; a second access line coupled to a second memory cell for replacing the first memory cell when the first memory cell is a failure memory cell; a first driving block coupled to one of the first access line and the second access line, and suitable for driving said one of the first access line and the second access line with a first voltage when the first memory cell is accessed; and a first repair coupling block suitable for selectively coupling the first access line and the second access line based on whether the first memory cell is a failure memory cell or not when the first memory cell is accessed.
摘要翻译：一种包括半导体存储单元的电子设备，包括：耦合到第一存储单元的第一存取线; 耦合到第二存储单元的第二存取线，用于在所述第一存储单元是故障存储单元时替换所述第一存储单元; 第一驱动块，耦合到第一接入线路和第二接入线路之一，并且适于在接入第一存储器单元时以第一电压驱动第一接入线路和第二接入线路中的所述一个; 以及第一修复耦合块，适于在访问第一存储器单元时基于第一存储单元是否是故障存储单元来选择性地耦合第一存取线和第二存取线。

34. 发明授权

US09293227B1 Semiconductor memory apparatus and semiconductor integrated circuit apparatus 有权
标题翻译：半导体存储装置和半导体集成电路装置
公开(公告)号：US09293227B1
公开(公告)日：2016-03-22
申请号：US14797190
申请日：2015-07-13
申请人： Powerchip Technology Corporation
发明人： Atsushi Takasugi
IPC分类号： G11C16/04 , G11C29/00 , G11C17/16 , G11C17/18
CPC分类号： G11C29/76 , G11C16/04 , G11C29/78 , G11C29/82
摘要： A memory control circuit 10 controls an operation of reading stored data from a memory cell 50 connected to a word line WL and a bit line BL based on an address Address including a row address Ax and a column address Ay. When the address Address includes redundancy addresses P1 to P4 designating a word line WLa or a bit line BLc connected to a specific memory cell Cc, redundancy decoders 13-1 to 13-4 replace the specific memory cell Cc with a redundancy memory cell RCc connected to redundancy word lines RWL1 and RWL2 or redundancy bit lines RBL1 and RBL2. Redundancy address latch circuits 12-1 to 12-4 respectively hold the redundancy addresses P1 to P4, and erase the held redundancy addresses P1 to P4 based on a reset signal RS inputted from the memory control circuit 10.
摘要翻译：存储器控制电路10基于包括行地址Ax和列地址Ay的地址地址来控制从连接到字线WL和位线BL的存储单元50读取存储的数据的操作。当地址地址包括指定字线WLa的冗余地址P1至P4或连接到特定存储单元Cc的位线BLc时，冗余解码器13-1至13-4用连接的冗余存储单元RCc代替特定存储单元Cc 到冗余字线RWL1和RWL2或冗余位线RBL1和RBL2。冗余地址锁存电路12-1至12-4分别保持冗余地址P1至P4，并且基于从存储器控制电路10输入的复位信号RS来擦除保持的冗余地址P1至P4。

35. 发明授权

US09257158B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09257158B2
公开(公告)日：2016-02-09
申请号：US14328324
申请日：2014-07-10
申请人： SK hynix Inc.
发明人： Hong-Jung Kim
IPC分类号： G11C7/00 , G11C7/10 , G11C29/00
CPC分类号： G11C29/78 , G11C7/10 , G11C17/16 , G11C17/18 , G11C29/00 , G11C29/785
摘要： A semiconductor device includes: a plurality of repair fuse circuits configured to each program a repair target address; and an enable signal generation circuit configured to generate at least one enable signal in response to a source signal and provide the enable signal to each of the repair fuse circuits in common. Since the semiconductor device may iteratively generate a rupture enable signal through a feedback scheme, the area occupied by a circuit, such as a shift register or a D flip-flop may be saved.
摘要翻译：半导体器件包括：多个修复熔丝电路，其被配置为对每个修复目标地址进行编程; 以及使能信号生成电路，被配置为响应于源极信号产生至少一个使能信号，并将所述使能信号提供给每个所述修复熔丝电路。由于半导体器件可以通过反馈方案迭代地产生断裂使能信号，因此可以节省诸如移位寄存器或D触发器的电路所占据的面积。

36. 发明申请

US20160035438A1 MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：包括其的存储器件和存储器系统
公开(公告)号：US20160035438A1
公开(公告)日：2016-02-04
申请号：US14567561
申请日：2014-12-11
申请人： SK hynix Inc.
发明人： Kwi-Dong KIM
IPC分类号： G11C29/00 , G11C17/16
CPC分类号： G11C29/78 , G11C17/16 , G11C29/4401 , G11C2029/4402
摘要： A memory device includes a non-volatile memory circuit suitable for storing system hard repair data, a temporary memory circuit suitable for storing system soft repair data, a system register circuit suitable for receiving and storing the system hard repair data or the system soft repair data during a boot-up operation, and a memory bank suitable for performing a repair operation based on first data stored in the system register circuit.
摘要翻译：存储装置包括适用于存储系统硬修复数据的非易失性存储器电路，适于存储系统软修复数据的临时存储电路，适用于接收和存储系统硬修复数据或系统软修复数据的系统寄存器电路以及适于基于存储在系统寄存器电路中的第一数据执行修复操作的存储体。

37. 发明申请

US20150340077A1 APPARATUSES AND METHODS FOR CONTROLLING REFRESH OPERATIONS 有权
标题翻译：控制刷新操作的装置和方法
公开(公告)号：US20150340077A1
公开(公告)日：2015-11-26
申请号：US14713942
申请日：2015-05-15
申请人： MICRON TECHNOLOGY, INC.
发明人： HIROSHI AKAMATSU
IPC分类号： G11C11/408 , G11C29/00
CPC分类号： G11C11/408 , G11C5/04 , G11C5/063 , G11C8/12 , G11C29/18 , G11C29/78
摘要： An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.
摘要翻译：一种装置包括第一字线，第二字线和控制器。第二个字线与第一个字线相邻。控制电路包括第一缺陷地址存储电路和第一检测电路。第一缺陷地址存储电路存储第一使能信息以及第一缺陷地址。第一使能信息指示第二字线是否正常。当第一字线被访问时，第一检测电路提供第一信号。第一信号指示第二字线是否正常。当第一信号指示第二字线正常工作时，控制电路激活第二字线，并且当第一信号指示第二字线不起作用时，控制电路不激活第二字线。

38. 发明申请

US20150213863A1 SUB-BLOCK DISABLING IN 3D MEMORY 有权
标题翻译：三维存储器中的子块禁用
公开(公告)号：US20150213863A1
公开(公告)日：2015-07-30
申请号：US14682762
申请日：2015-04-09
申请人： Micron Technology, Inc.
发明人： Chang Wan Ha
IPC分类号： G11C8/12 , G11C8/08
CPC分类号： G11C8/12 , G11C8/06 , G11C8/08 , G11C11/5621 , G11C16/08 , G11C16/20 , G11C29/00 , G11C29/04 , G11C29/76 , G11C29/765 , G11C29/78 , G11C29/832
摘要： Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described.
摘要翻译：一些实施例涉及与存储器单元的块相关联的装置和方法。存储器单元的块可以包括存储器单元的两个或更多个子块。一个这样的子块可以包括包括选择晶体管的存储单元的垂直串。装置可以包括子块禁止电路。子块禁止电路可以包括内容寻址存储器。内容可寻址存储器可以接收包括块地址和子块地址的地址。如果接收到的地址包括块地址和与标记子块相关联的子块地址，则内容可寻址存储器可以输出信号以禁用标记子块。子块禁止电路还可以包括多个驱动器，以基于该信号来驱动一个或多个选择晶体管。描述其他装置和方法。

39. 发明申请

US20150187436A1 INTEGRATED CIRCUIT DEFECT DETECTION AND REPAIR 有权
标题翻译：集成电路缺陷检测和维修
公开(公告)号：US20150187436A1
公开(公告)日：2015-07-02
申请号：US14320164
申请日：2014-06-30
申请人： INTEL CORPORATION
发明人： Bruce QUERBACH , William K. LUI , David G. ELLIS , David J. ZIMMERMAN , Theodore Z. SCHOENBORN , Christopher W. HAMPSON , Ifar WAN , Yulan ZHANG
IPC分类号： G11C29/10 , G06F11/27 , G06F11/263
CPC分类号： G11C29/38 , G06F11/263 , G06F11/27 , G11C11/406 , G11C29/10 , G11C29/1201 , G11C29/16 , G11C29/18 , G11C29/20 , G11C29/36 , G11C29/4401 , G11C29/72 , G11C29/78 , G11C29/783 , G11C2029/1202 , G11C2029/1204 , G11C2029/1206 , G11C2029/1208 , G11C2029/3602 , G11C2029/4402
摘要： In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets. Other aspects are described herein.
摘要翻译：根据本说明书，装置包括内部缺陷检测和修复电路，其包括内置于装置内的自检逻辑电路和内置在装置内的自修复逻辑电路。在一个实施例中，内置自检逻辑电路可以被配置为自动识别存储器中的有缺陷的存储器单元。在识别一个或多个有缺陷的存储器单元时，内置的自修复逻辑电路可以被配置为通过用存储器内的备用单元替换有缺陷的单元来自动修复有缺陷的存储器单元。在一个实施例中，作为存储器地址和周期性地址偏移的函数产生数据模式。本文描述了其它方面。

40. 发明申请

US20150098286A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20150098286A1
公开(公告)日：2015-04-09
申请号：US14106831
申请日：2013-12-15
申请人： SK hynix Inc.
发明人： Doo-Chan LEE , Byeong-Chan CHOI , One-Gyun NA
IPC分类号： G11C29/00 , G11C29/04
CPC分类号： G11C29/76 , G11C11/408 , G11C17/16 , G11C17/18 , G11C29/04 , G11C29/765 , G11C29/78 , G11C29/785 , G11C29/808 , G11C2029/4402
摘要： A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information.
摘要翻译：半导体存储器件包括：具有多个正常细胞系和多个修复细胞系的存储单元阵列区域; 适合于分别响应于本地地址选择所述多个正常细胞系的多个正常细胞系选择单元; 多个修复细胞系选择单元，分别适于选择多个修复细胞系，代替对应于本地地址的失败信息的正常细胞系选择单元; 保险丝驱动单元，包括其中编程了故障信息的熔丝阵列，适合于禁用对应于故障信息的正常单元行选择单元，以及启用与故障信息无关的正常单元行选择单元; 以及地址确定单元，其适于基于所述失败信息来控制所述多个修复单元线选择单元。

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