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31. 发明授权

US09600431B2 High performance interconnect physical layer 有权
公开(公告)号：US09600431B2
公开(公告)日：2017-03-21
申请号：US13976919
申请日：2013-03-15
申请人： Intel Corporation
发明人： Venkatraman Iyer , Darren S. Jue , Sitaraman V. Iyer
IPC分类号： G06F13/42 , G06F13/40 , G06N99/00
CPC分类号： G06F13/4004 , G06F13/4221 , G06N99/005 , Y02D10/14 , Y02D10/151
摘要： A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.

32. 发明授权

US09477615B1 Bi-directional low latency bus mode 有权
标题翻译：双向低延迟总线模式
公开(公告)号：US09477615B1
公开(公告)日：2016-10-25
申请号：US12539308
申请日：2009-08-11
申请人： Gal Basson , Tal Azogui
发明人： Gal Basson , Tal Azogui
IPC分类号： G06F13/00 , G06F13/20 , H04B1/38 , H04W4/00 , G06F13/12
CPC分类号： G06F13/00 , G06F13/20 , G06F13/4004 , H04B1/38 , H04W4/00
摘要： A method for low latency data transfers between a wireless root device and a wireless endpoint device connected through a wireless peripheral-interconnect bus. The method comprises setting the wireless root device and the wireless endpoint device to operate in bi-directional low latency bus (BDLLB) mode; generating, by the wireless root device, a first data frame to be transmitted to the end-point device, wherein the first data frame includes at least a preamble, a block acknowledgment (ACK) frame and aggregation of a plurality of medium access control service data units (MSDUs) according to an order they received from a data link layer of the wireless peripheral-interconnect bus; and transmitting the first data frame to the wireless endpoint device over a wireless medium.
摘要翻译：一种用于通过无线外设互连总线连接的无线根设备和无线终端设备之间的低延迟数据传输的方法。该方法包括将无线根设备和无线终端设备设置为以双向低延迟总线（BDLLB）模式工作; 通过所述无线根设备产生要发送到所述终点设备的第一数据帧，其中所述第一数据帧至少包括前导码，块确认（ACK）帧和多个媒体访问控制服务的聚合数据单元（MSDU），根据其从无线外设互连总线的数据链路层接收的顺序; 以及通过无线介质将所述第一数据帧发送到所述无线终端设备。

33. 发明申请

US20160147684A1 IN-BAND INTERRUPT TIME STAMP 有权
标题翻译：内插中断时间戳
公开(公告)号：US20160147684A1
公开(公告)日：2016-05-26
申请号：US14949534
申请日：2015-11-23
申请人： QUALCOMM Incorporated
发明人： Shoichiro Sengoku
IPC分类号： G06F13/366 , G06F13/40 , G06F13/42 , G06F13/362
CPC分类号： G06F13/24 , G06F1/14 , G06F13/3625 , G06F13/366 , G06F13/4004 , G06F13/4282
摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A method performed by a slave device coupled to a serial bus includes detecting an event related to a function of the slave device, initiating a first counter in the slave device, asserting an in-band interrupt request by driving at least one signal on the serial bus, and transmitting content of the first counter to a bus master coupled to the serial bus during an interrupt handling procedure. The first counter may count cycles of a clock used by the slave device or occurrences of a signaling state or condition on the serial bus. The content of the first counter may be used to determine a time stamp for the event.
摘要翻译：描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。由耦合到串行总线的从设备执行的方法包括检测与从设备的功能有关的事件，启动从设备中的第一计数器，通过驱动串行的至少一个信号来断言带内中断请求总线，以及在中断处理过程期间将第一计数器的内容发送到耦合到串行总线的总线主机。第一个计数器可以计数由从设备使用的时钟的周期或串行总线上的信令状态或状态的发生。第一计数器的内容可以用于确定事件的时间戳。

34. 发明授权

US09152595B2 Processor-based system hybrid ring bus interconnects, and related devices, processor-based systems, and methods 有权
标题翻译：基于处理器的系统混合环形总线互连以及相关设备，基于处理器的系统和方法
公开(公告)号：US09152595B2
公开(公告)日：2015-10-06
申请号：US13654653
申请日：2012-10-18
申请人： QUALCOMM Incorporated
发明人： Jaya Prakash Subramaniam Ganasan , Mark Michael Schaffer , Prudhvi N. Nooney , Perry Willmann Remaklus, Jr.
IPC分类号： G06F1/32 , G06F13/40 , G06F15/173 , G06F13/368
CPC分类号： G06F13/4027 , G06F1/3287 , G06F13/368 , G06F13/4004 , G06F15/17375 , Y02D10/14 , Y02D10/151
摘要： Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided. The processor-based system hybrid ring bus interconnect includes multiple ring buses, each having a bus width and configured to receive bus transaction messages from a requester device(s). The processor-based system hybrid ring bus interconnect also includes an inter-ring router(s) coupled to the ring buses. The inter-ring router(s) is configured to dynamically direct bus transaction messages among the ring buses based on bandwidth requirements of the requester device(s). Thus, less power is consumed than by a crossbar interconnect due to simpler switching configurations. Further, the inter-ring router(s) allows for provision of multiple ring buses that can be dynamically activated and deactivated based on bandwidth requirements. This provides conservation of power when full bandwidth requirements on the processor-based system hybrid ring bus interconnect are not required.
摘要翻译：公开了基于处理器的系统混合环形总线互连以及相关设备，系统和方法。在一个实施例中，提供了基于处理器的系统混合环形总线互连。基于处理器的系统混合环形总线互连包括多个环形总线，每个环形总线具有总线宽度并且被配置为从请求者设备接收总线事务消息。基于处理器的系统混合环形总线互连还包括耦合到环形总线的环形间路由器。环形路由器被配置为基于请求者设备的带宽需求来动态地指导环形总线中的总线事务消息。因此，由于更简单的开关配置，功率消耗比交叉开关互连更少。此外，环形路由器允许提供可以基于带宽需求被动态地激活和去激活的多个环形总线。当不需要基于处理器的系统混合环形总线互连的全带宽要求时，这提供了功率的保护。

35. 发明申请

US20150205741A1 HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER 审中-公开
标题翻译：高性能互连物理层
公开(公告)号：US20150205741A1
公开(公告)日：2015-07-23
申请号：US14672107
申请日：2015-03-28
申请人： Intel Corporation
发明人： Venkatraman Iyer , Darren S. Jue , Sitaraman V. Iyer
IPC分类号： G06F13/40 , G06N99/00
CPC分类号： G06F13/4004 , G06F13/4221 , G06N99/005 , Y02D10/14 , Y02D10/151
摘要： A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.
摘要翻译：生成一组训练序列，每个训练序列包括相应的训练序列头部，训练序列头部将在训练序列集合上进行DC平衡。训练序列的集合可以与电子有序集合组合以形成用于诸如链路适配，链路状态转换，字节锁定，偏斜校正和其他任务之类的任务的超序列。

36. 发明授权

US09003083B2 Buffer circuit and semiconductor integrated circuit 有权
标题翻译：缓冲电路和半导体集成电路
公开(公告)号：US09003083B2
公开(公告)日：2015-04-07
申请号：US14222367
申请日：2014-03-21
申请人： Fujitsu Semiconductor Limited
发明人： Ryuji Kojima
IPC分类号： G06F3/00 , G06F5/00 , G06F3/06
CPC分类号： G06F13/4004
摘要： A buffer circuit includes: a register array including registers in a plurality of stages; and a control circuit configured to rearrange a plurality of pieces of received data in the register in a determined transfer order and to control the register array to sequentially output the plurality of pieces of received data as one piece of transfer data when all the received data is stored, wherein the control circuit controls the register array to store stored data in each register in a preceding stage when the register array outputs the received data, and the control circuit determines a write register in accordance with the transfer order when the register array newly stores the received data and controls the register array to store data stored in the write register in a following stage of the write register and to store the new received data in the write register.
摘要翻译：缓冲电路包括：包括多级寄存器的寄存器阵列; 以及控制电路，被配置为以确定的传送顺序重新布置所述寄存器中的多个接收数据，并且当所有接收到的数据都是所述接收数据时，控制所述寄存器阵列顺序地输出所述多条接收数据作为一条传送数据存储，其中当寄存器阵列输出接收到的数据时，控制电路控制寄存器阵列以在前一级存储每个寄存器中的存储数据，并且当寄存器阵列新存储时，控制电路根据传送顺序确定写入寄存器接收到的数据并且控制寄存器阵列以将写入寄存器中存储的数据存储在写入寄存器的后一级中，并将新的接收数据存储在写入寄存器中。

37. 发明申请

US20150046614A1 CENTRALIZED PERIPHERAL ACCESS PROTECTION 有权
标题翻译：集中的外围访问保护
公开(公告)号：US20150046614A1
公开(公告)日：2015-02-12
申请号：US13965020
申请日：2013-08-12
申请人： Frode Milch PEDERSEN , Sebastien JOUIN , Stein DANIELSEN , Francois FOSSE , Thierry DELALANDE , Ivar HOLAND , James HALLMAN
发明人： Frode Milch PEDERSEN , Sebastien JOUIN , Stein DANIELSEN , Francois FOSSE , Thierry DELALANDE , Ivar HOLAND , James HALLMAN
IPC分类号： G06F13/362 , G06F13/40
CPC分类号： G06F9/526 , G06F11/00 , G06F11/004 , G06F13/122 , G06F13/28 , G06F13/362 , G06F13/4004 , G06F13/4282 , G06F17/30362 , G06F2201/825
摘要： Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.
摘要翻译：公开了针对被配置为保护系统中的一个或多个外围组件的中央外围设备访问控制器（PAC）的实现。在一些实现中，PAC存储可以由软件设置或清除的数据。该数据对应于被路由到对应的外围组件的PAC的输出信号。当数据指示外设“未锁定”时，PAC将允许写入传输到外设组件中的寄存器。当数据指示外设组件“锁定”时，PAC将拒绝对外设组件中的寄存器进行写入传输，并以错误结束。

38. 发明授权

US08943256B1 Serial data intermediary device, and related systems and methods 有权
标题翻译：串行数据中介设备及相关系统及方法
公开(公告)号：US08943256B1
公开(公告)日：2015-01-27
申请号：US14133359
申请日：2013-12-18
申请人： Cypress Semiconductor Corporation
发明人： Gregory J. Landry , Edward L. Grivna
IPC分类号： G06F13/36 , G06F13/38 , G06F13/40 , G06F13/42
CPC分类号： G06F13/4004 , G06F13/385 , G06F13/404 , G06F13/4045 , G06F13/4054 , G06F13/4282 , G06F2213/0016 , G06F2213/0052
摘要： An integrated circuit (IC) device can include a serial communication first interface (I/F) circuit electrically coupled to first physical connections of the IC device, and configured to respond to communication signals received at the first physical connections; at least one serial communication second interface (I/F) circuit electrically coupled to second physical connections of the IC device, and configured to enable data transactions over the second physical connections; and a repeater circuit configured to bypass the first I/F circuit and enable serial communication signals to be transmitted from the first physical connections to the second physical connections. Systems including such an IC device and related methods are also disclosed.
摘要翻译：集成电路（IC）装置可以包括电耦合到IC器件的第一物理连接并被配置为响应在第一物理连接处接收的通信信号的串行通信第一接口（I / F）电路; 至少一个串行通信第二接口（I / F）电路，其电耦合到所述IC设备的第二物理连接，并且被配置为允许通过所述第二物理连接进行数据交易; 以及中继器电路，被配置为绕过所述第一I / F电路并且使串行通信信号能够从所述第一物理连接发送到所述第二物理连接。还公开了包括这种IC器件和相关方法的系统。

39. 发明申请

US20140297906A1 BUFFER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：缓冲电路和半导体集成电路
公开(公告)号：US20140297906A1
公开(公告)日：2014-10-02
申请号：US14222367
申请日：2014-03-21
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Ryuji KOJIMA
IPC分类号： G06F3/06
CPC分类号： G06F13/4004
摘要： A buffer circuit includes: a register array including registers in a plurality of stages; and a control circuit configured to rearrange a plurality of pieces of received data in the register in a determined transfer order and to control the register array to sequentially output the plurality of pieces of received data as one piece of transfer data when all the received data is stored, wherein the control circuit controls the register array to store stored data in each register in a preceding stage when the register array outputs the received data, and the control circuit determines a write register in accordance with the transfer order when the register array newly stores the received data and controls the register array to store data stored in the write register in a following stage of the write register and to store the new received data in the write register.
摘要翻译：缓冲电路包括：包括多级寄存器的寄存器阵列; 以及控制电路，被配置为以确定的传送顺序重新布置所述寄存器中的多个接收数据，并且当所有接收到的数据都是所述接收数据时，控制所述寄存器阵列顺序地输出所述多条接收数据作为一条传送数据存储，其中当寄存器阵列输出接收到的数据时，控制电路控制寄存器阵列以在前一级存储每个寄存器中的存储数据，并且当寄存器阵列新存储时，控制电路根据传送顺序确定写入寄存器接收到的数据并且控制寄存器阵列以将写入寄存器中存储的数据存储在写入寄存器的后一级中，并将新的接收数据存储在写入寄存器中。

40. 发明申请

US20140281103A1 INFORMATION PROCESSING APPARATUS AND METHOD FOR GENERATING COUPLING INFORMATION 有权
标题翻译：信息处理装置和联合信息的产生方法
公开(公告)号：US20140281103A1
公开(公告)日：2014-09-18
申请号：US14161019
申请日：2014-01-22
申请人： FUJITSU LIMITED
发明人： Atsushi NAGASE
IPC分类号： G06F13/40
CPC分类号： G06F13/4072 , G06F13/16 , G06F13/4004 , H04L12/40 , H04L12/40078
摘要： A processing apparatus includes a memory, and a processor coupled to the memory and configured to acquire first data that indicates correspondence relationship between a first address given to a first adapter of a first device and a first bus number given to a first bus coupled to the first adapter, acquire second data that indicates correspondence relationship between a second address given to a second adapter of a first device and a second bus number given to a second bus coupled to the second adapter, acquire third data that indicates correspondence relationship between the first address and a port number given to a port of a second device, the port being coupled to the first adapter with the first bus, and when the second bus number is identical to the first bus number, generate fourth data that indicates that the second adapter is coupled to the port.
摘要翻译：一种处理装置，包括存储器和处理器，其耦合到存储器并且被配置为获取指示给予第一设备的第一适配器的第一地址与给予耦合到第一设备的第一总线的第一总线号之间的对应关系的第一数据第一适配器，获取指示给予第一设备的第二适配器的第二地址与给予耦合到第二适配器的第二总线的第二总线号之间的对应关系的第二数据，获取指示第一地址以及给予第二设备的端口的端口号，所述端口利用所述第一总线耦合到所述第一适配器，并且当所述第二总线号码与所述第一总线号码相同时，生成指示所述第二适配器为加上港口。

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