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31. 发明授权

US07284074B2 Pipelined network processing with FIFO queues 有权
标题翻译：使用FIFO队列进行流水线网络处理
公开(公告)号：US07284074B2
公开(公告)日：2007-10-16
申请号：US10286361
申请日：2002-10-31
申请人： Eugene Lee , Cong Ye , Peter Chang , Ajoy Aswadhati
发明人： Eugene Lee , Cong Ye , Peter Chang , Ajoy Aswadhati
IPC分类号： G06F5/00 , G06F3/00 , G06F13/00
CPC分类号： H04L49/9068 , H04L49/90 , H04L69/12
摘要： A system and method for operating on data within a network device is described. Between two data operations in a network device is a FIFO queue, which is used to separate the clock domains of the data operations. Data from the first operation is stored in the FIFO queue, which signals an indication to the second operation that there is data in the queue. When the second operation is signaled that there is data in the FIFO queue, it immediately begins reading data from the queue, and begins performing its prescribed operations on the data once it has read enough data from the queue for it to begin operating.
摘要翻译：描述了用于对网络设备内的数据进行操作的系统和方法。在网络设备中的两个数据操作之间是FIFO队列，用于分离数据操作的时钟域。来自第一操作的数据被存储在FIFO队列中，其向第二操作发出指示队列中存在数据的指示。当第二个操作发信号通知FIFO队列中有数据时，它立即从队列开始读取数据，并且一旦从队列中读取足够的数据以开始运行，就开始对数据执行其规定的操作。

32. 发明授权

US07274696B1 Scalable redundant switch fabric architecture 有权
标题翻译：可扩展冗余交换矩阵架构
公开(公告)号：US07274696B1
公开(公告)日：2007-09-25
申请号：US10278158
申请日：2002-10-21
申请人： Somsubhra Sikdar
发明人： Somsubhra Sikdar
IPC分类号： H04L12/28 , H04L12/50
CPC分类号： H04L49/45 , H04L45/60 , H04L49/1523
摘要： A high-speed router and method for operation of the core of such a router are disclosed. The disclosure describes routing packets from core input ports to core output ports by aggregating or queuing packets at router core ingress ports in queues designated for common router core egress ports. A scheduler selects a set of queues, up to one per ingress port, for switching through the router core at each epoch (an epoch is a time slice). When the epoch for a given set of queues arrives, data from each queue is stranded, with one strand sent to each of multiple switch fabric cards. The switch fabric cards operate in parallel to switch the strands from that queue to a common egress port (as configured by the scheduler), where the strands are recombined to reconstruct the original queue data. This architecture can be made fault tolerant, can be made to degrade gracefully when one or more switch fabric cards goes down, and can support increased traffic simply by expanding the number of switch fabric cards. Scheduling for the router core is greatly simplified as compared to a core that switches on a packet-by-packet or cell basis, which also allows higher traffic loads.
摘要翻译：公开了一种用于操作这种路由器的核心的高速路由器和方法。本公开描述了通过在为通用路由器核心出口端口指定的队列中的路由器核心入口端口聚合或排队分组，将分组从核心输入端口路由到核心输出端口。调度器选择一组队列，每个入口端口最多一个，用于在每个时期切换路由器内核（时代是时间片）。当给定的一组队列的时期到达时，来自每个队列的数据被搁置，其中一条发送到多个交换机组卡中的每一个。交换矩阵卡并行操作，将线从该队列切换到公共出口（由调度器配置），其中线重新组合以重建原始队列数据。这种架构可以做到容错，可以在一个或多个交换矩阵卡掉电时正常地降级，并且可以通过扩展交换矩阵卡的数量来支持增加的流量。与基于逐个分组或小区的核心相比，路由器核心的调度大大简化，这也允许更高的流量负载。

33. 发明授权

US07154902B1 Epoch-based packet switching 有权
标题翻译：基于时代的分组交换
公开(公告)号：US07154902B1
公开(公告)日：2006-12-26
申请号：US10277577
申请日：2002-10-21
申请人： Somsubhra Sikdar
发明人： Somsubhra Sikdar
IPC分类号： H04L12/28
CPC分类号： H04L49/254 , H04L45/02 , H04L45/60 , H04L49/1523 , H04L49/251
摘要： A high-speed router and method for operation of the core of such a router are disclosed. A switch fabric serves a plurality of ingress and egress ports. Packets are sorted into queues at each ingress port, each queue corresponding to one of the egress ports. Queue status information for each ingress port is communicated to a central scheduler. The scheduler reconfigures the switch fabric to a new port mapping once per epoch, where an epoch is long enough to allow each ingress port to transmit a large plurality of queued packets. The scheduler also sends port mapping information to the ingress ports, so that those ports can match one of their queues with the egress port mapping for each epoch. The switch fabric can achieve extremely high throughput since it doesn't recognize and switch packets per se, but deals with large multi-packet blocks that can be efficiently scheduled by the central scheduler.
摘要翻译：公开了一种用于操作这种路由器的核心的高速路由器和方法。交换结构为多个入口和出口提供服务。分组在每个入口端口分类为队列，每个队列对应一个出口端口。每个入口端口的队列状态信息被传送到中央调度器。调度器将交换结构重新配置为每个时代一次的新端口映射，其中时期足够长以允许每个入口端口发送大量排队的分组。调度程序还将端口映射信息发送到入口端口，以便这些端口可以将其一个队列与每个时隙的出口端口映射相匹配。交换结构可以实现极高的吞吐量，因为它不能识别和切换数据包本身，而是处理可以由中央调度器有效调度的大型多分组块。

34. 发明授权

US06944159B1 Method and apparatus for providing virtual point to point connections in a network 有权
标题翻译：用于在网络中提供虚拟点对点连接的方法和装置
公开(公告)号：US06944159B1
公开(公告)日：2005-09-13
申请号：US09834485
申请日：2001-04-12
申请人： Shivi Fotedar , Rajeev V. Manur , Somsubhra Sikdar
发明人： Shivi Fotedar , Rajeev V. Manur , Somsubhra Sikdar
IPC分类号： H04J3/16 , H04L12/28
CPC分类号： H04L45/38 , H04L12/462 , H04L45/66
摘要： Transparent point-to-point connectivity is provided between an incoming interface on an ingress node and an outgoing interface on an egress node in a network. An address associated with the egress node is circulated to the nodes in the network and a next hop address toward the egress node address is determined at each node. A label value is circulated along with the egress node address to the nodes. Examples of label values can include VLAN Ids or Multi-protocol Label Switching (MPLS) labels. If data is received having the label value, the node receiving the data identifies the next hop address associated with that label value and transfers the data to the next hop associated with the identified next hop address.
摘要翻译：入口节点的入接口和网络中出口节点的出接口之间提供透明的点对点连接。与出口节点相关联的地址被循环到网络中的节点，并且在每个节点处确定朝向出口节点地址的下一跳地址。标签值与出口节点地址一起传播到节点。标签值的示例可以包括VLAN ID或多协议标签交换（MPLS）标签。如果接收到具有标签值的数据，则接收数据的节点识别与该标签值相关联的下一跳地址，并将该数据传送到与所识别的下一跳地址相关联的下一跳。

35. 发明授权

US10320714B2 Distributed packet switch having a wireless control plane 有权
公开(公告)号：US10320714B2
公开(公告)日：2019-06-11
申请号：US15246198
申请日：2016-08-24
申请人： FORCE10 NETWORKS, INC
发明人： Joel R. Goergen
IPC分类号： H04L12/931 , H04L12/64 , H04W56/00 , H04W72/12 , H04W28/02 , H04W28/18
摘要： A packet network device such as a network switch includes a number of functional cards or chassis modules at least some of which are connected to both an electrical backplane and a wireless backplane. The electrical backplane provides data plane signal paths and the wireless backplane provides control plane signal paths.

36. 发明授权

US09705824B2 Intelligent chassis management 有权
公开(公告)号：US09705824B2
公开(公告)日：2017-07-11
申请号：US14622267
申请日：2015-02-13
申请人： Force10 Networks, Inc.
发明人： David K. Wong
IPC分类号： H04L12/403 , H04L12/931 , G08B21/18 , H04J3/04 , H04J3/24 , G06F15/16
CPC分类号： H04L49/40 , G06F15/161 , G08B21/18 , H04J3/047 , H04J3/247 , H04L12/403
摘要： A modular system uses point-to-point communication between field-programmable gate arrays (FPGAs) on a control module and each port module, respectively, to manage basic module functions, such as power, environmental monitoring, and health checks on the modules and their components. This allows a chassis to be managed without fully powering each card first, frees processors on the modules from having to perform health checks, allows dedicated resources to rapidly monitor the health of each card, and prevents one bad card from disabling management of all cards.

37. 发明授权

US09560774B2 Method of fabricating a circuit board 有权
标题翻译：制造电路板的方法
公开(公告)号：US09560774B2
公开(公告)日：2017-01-31
申请号：US13420167
申请日：2012-03-14
申请人： Joel R. Goergen , Greg Hunt
发明人： Joel R. Goergen , Greg Hunt
IPC分类号： H05K3/20 , H05K3/42 , H05K1/02 , H05K3/00
CPC分类号： H05K3/429 , H05K1/0216 , H05K1/0237 , H05K3/0047 , H05K2201/044 , H05K2201/09236 , H05K2201/09845 , H05K2203/0207 , H05K2203/0242 , H05K2203/175 , Y10T29/49165
摘要： A high-speed router backplane is disclosed. The router backplane uses differential signal pairs on multiple signal layers, each sandwiched between a pair of digital ground layers. Thru-holes are used to connect the differential signal pairs to external components. To reduce routing complexity, at least some of the differential signal pairs route through a via pair, somewhere along their path, to a different signal layer. At least some of the thru-holes and vias are drilled to reduce an electrically conductive stub length portion of the hole. The drilled portion of a hole includes a transition from a first profile to a second profile to reduce radio frequency reflections from the end of the drilled hole.
摘要翻译：公开了一种高速路由器背板。路由器背板在多个信号层上使用差分信号对，每个信号对夹在一对数字接地层之间。通孔用于将差分信号对连接到外部组件。为了降低路由复杂度，差分信号对中的至少一些在其路径的某处沿着不同的信号层路由通路对。钻出至少一些通孔和通孔以减少孔的导电短截线长度部分。孔的钻孔部分包括从第一轮廓到第二轮廓的转变，以减少从钻孔的端部的射频反射。

38. 发明授权

US09077607B2 Border gateway protocol inbound policy optimization 有权
标题翻译：边界网关协议入站策略优化
公开(公告)号：US09077607B2
公开(公告)日：2015-07-07
申请号：US12842242
申请日：2010-07-23
申请人： Kalpesh Zinjuwadia , Srikanth Rao
发明人： Kalpesh Zinjuwadia , Srikanth Rao
IPC分类号： H04L12/66 , H04L29/06 , G06F15/16 , G06F15/173 , H04L12/751 , H04L12/741 , H04L12/721 , H04L12/813 , H04L12/715
CPC分类号： H04L45/02 , H04L29/06578 , H04L45/04 , H04L45/44 , H04L45/745 , H04L47/20 , H04L63/0227
摘要： A BGP capable packet network device is located at the boundary of an autonomous network and in communication with a peer BGP capable packet network device in a neighboring autonomous network. The BGP capable packet network device is comprised of one or more line cards for receiving and, processing and sending packets of information, and for receiving and forwarding routing update information to a route processor comprising the packet network device. The route processor runs a border gateway protocol which is configured with one or more policies that operate to filter the routing update information received from the line card. The routing update information filter is comprised of at least one variable length path attribute and the filter operates such that it only applies the variable length path attribute one time to the routing update information.
摘要翻译：一个BGP能力的分组网络设备位于自治网络的边界，并与相邻自治网络中的具有对等BGP功能的分组网络设备进行通信。 BGP功能的分组网络设备由一个或多个线卡组成，用于接收和处理和发送信息包，并且用于接收和转发路由更新信息到包括分组网络设备的路由处理器。路由处理器运行边界网关协议，其配置有一个或多个策略，用于对从线卡接收的路由更新信息进行过滤。路由更新信息过滤器由至少一个可变长度路径属性组成，并且过滤器操作，使得其仅将一次可变长度路径属性应用于路由更新信息。

39. 发明授权

US08804751B1 FIFO buffer with multiple stream packet segmentation 有权
标题翻译：具有多个流分组分段的FIFO缓冲器
公开(公告)号：US08804751B1
公开(公告)日：2014-08-12
申请号：US11537958
申请日：2006-10-02
申请人： Glenn Poole , Brad Danofsky , David Haddad , Ann Gui , Heeloo Chung , Joanna Lin
发明人： Glenn Poole , Brad Danofsky , David Haddad , Ann Gui , Heeloo Chung , Joanna Lin
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/021 , H04L47/365 , H04L49/90 , H04L49/9021 , H04L49/9057
摘要： An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.
摘要翻译：一个基于时代的网络处理器内部地划分数据包，用于处理和聚合在时代有效载荷中。 FIFO缓冲区与存储器管理单元交互以有效地管理分段和聚合过程。

40. 发明授权

US08780911B2 Link aggregation based on port and protocol combination 有权
标题翻译：基于端口和协议组合的链路聚合
公开(公告)号：US08780911B2
公开(公告)日：2014-07-15
申请号：US12900435
申请日：2010-10-07
申请人： Janardhanan P. Narasimhan
发明人： Janardhanan P. Narasimhan
IPC分类号： H04L12/28
CPC分类号： H04L45/245 , H04L47/125 , H04L49/30 , H04L49/35 , H04L49/354 , Y02D50/30
摘要： A network switch suitable for receiving packets of information from and the packets of information to a communications network includes a plurality of physical ports, packet processing functionality and memory. The packet processing functionality operates on information stored in memory to determine the LAG, from among two or more LAGs, over which a packet received by the switch should be correctly forwarded. The switch memory stores a plurality of LAG tables, each one of which can include one or more entries comprising a physical port number and a packet parameter that are used by the packet processing functionality to determinately identify the correct LAG over which to forward a packet.
摘要翻译：适合于从通信网络接收信息包和信息包的网络交换机包括多个物理端口，分组处理功能和存储器。分组处理功能对存储在存储器中的信息进行操作以确定来自两个或更多个LAG中的LAG，由交换机接收到的分组应在其上正确转发。交换机存储器存储多个LAG表，每个LAG表可以包括一个或多个条目，该条目包括物理端口号和分组参数，该分组参数由分组处理功能用来确定地识别正确的转发分组的LAG。

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