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31. 发明授权

US09450045B1 Method for forming lateral super-junction structure 有权
标题翻译：形成横向超结结构的方法
公开(公告)号：US09450045B1
公开(公告)日：2016-09-20
申请号：US14747961
申请日：2015-06-23
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Madhur Bobde , Lingpeng Guan , Karthik Padmanabhan , Hamza Yilmaz
IPC分类号： H01L21/00 , H01L29/06 , H01L29/78 , H01L29/10 , H01L21/265 , H01L21/324
CPC分类号： H01L29/0634 , H01L21/26513 , H01L29/0623 , H01L29/0696 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/1095 , H01L29/7818
摘要： A fabrication method to form a lateral superjunction structure in a semiconductor device uses N and P type ion implantations into a base epitaxial layer. In some embodiments, the base epitaxial layer is an intrinsic epitaxial layer or a lightly doped epitaxial layer. The method performs simultaneous N and P type ion implantations into the base epitaxial layer. The epitaxial and implantation processes are repeated successively to form multiple implanted base epitaxial layers on a semiconductor base layer. After the desired number of implanted base epitaxial layers is formed, the semiconductor structure is subjected to annealing to form a lateral superjunction structure including alternate N and P type thin semiconductor regions. In particular, the alternating N and P type thin superjunction layers are formed by the ion implantation process and subsequent annealing. The fabrication method of the present invention ensures good charge control in the lateral superjunction structure.
摘要翻译：在半导体器件中形成横向超结构结构的制造方法使用N型和P型离子注入到基极外延层中。在一些实施例中，基底外延层是本征外延层或轻掺杂外延层。该方法同时进行N和P型离子注入到基底外延层中。连续重复外延和注入工艺以在半导体基底层上形成多个注入的基极外延层。在形成所需数量的注入基极外延层之后，对半导体结构进行退火以形成包括交替的N和P型薄半导体区域的横向超结构结构。特别地，通过离子注入工艺和随后的退火形成交替的N和P型薄超结层。本发明的制造方法确保了横向超结构结构中的良好的电荷控制。

32. 发明授权

US09443928B2 Oxide terminated trench MOSFET with three or four masks 有权
标题翻译：具有三个或四个掩模的氧化物端接沟槽MOSFET
公开(公告)号：US09443928B2
公开(公告)日：2016-09-13
申请号：US14965798
申请日：2015-12-10
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Sik Lui , Anup Bhalla
IPC分类号： H01L29/78 , H01L21/76 , H01L29/06 , H01L29/423 , H01L29/66 , H01L21/762 , H01L21/308 , H01L21/31 , H01L21/3213 , H01L27/088 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/45
CPC分类号： H01L29/7813 , H01L21/3081 , H01L21/31 , H01L21/32133 , H01L21/76224 , H01L27/088 , H01L29/0638 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/66666 , H01L29/66734 , H01L29/7811 , H01L29/7827
摘要： An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device.
摘要翻译：氧化物终端半导体器件可以包括多个栅极沟槽，栅极流道和绝缘体端接沟槽。栅极沟槽位于有源区域中。每个栅极沟槽包括导电栅电极。绝缘体端接沟槽位于围绕有源区域的端接区域中。绝缘体端接沟槽填充有绝缘体材料以形成用于半导体器件的绝缘子端子。

33. 发明授权

US09431495B2 Method of forming SGT MOSFETs with improved termination breakdown voltage 有权
标题翻译：形成具有改进的终止击穿电压的SGT MOSFET的方法
公开(公告)号：US09431495B2
公开(公告)日：2016-08-30
申请号：US14455150
申请日：2014-08-08
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Yongping Ding , Yeeheng Lee , Xiaobin Wang , Madhur Bobde
IPC分类号： H01L21/28 , H01L21/76 , H01L29/423 , H01L29/78 , H01L29/66
CPC分类号： H01L29/4236 , H01L29/407 , H01L29/66666 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/7827
摘要： A method of manufacturing a trench power MOSFET device with improved UIS performance and a high avalanche breakdown voltage is disclosed. The method includes performing a first etching of the epitaxial layer to form an active trench with an initial depth in an active area of the semiconductor substrate and a termination trench with a desired depth in a termination area of the semiconductor substrate, wherein the initial depth of the active trench is smaller than the desired depth of the termination trench and performing a second etching to increase the depth of the active trench to a desired depth wherein a depth difference between the desired depth of the active trench and the desired depth of the termination trench is smaller than a depth difference between the initial depth of the active trench and the desired depth of the termination trench.
摘要翻译：公开了一种制造具有改进的UIS性能和高雪崩击穿电压的沟槽功率MOSFET器件的方法。该方法包括执行外延层的第一蚀刻以形成在半导体衬底的有效区域中具有初始深度的有源沟槽和在半导体衬底的端接区域中具有期望深度的端接沟槽，其中初始深度有源沟槽小于终端沟槽的期望深度，并且执行第二蚀刻以将有源沟槽的深度增加到期望的深度，其中有源沟槽的期望深度与端接沟槽的期望深度之间的深度差小于有源沟槽的初始深度和端接沟槽的期望深度之间的深度差。

34. 发明授权

US09406661B2 Protection circuit including vertical gallium nitride schottky diode and PN junction diode 有权
标题翻译：保护电路包括垂直氮化镓肖特基二极管和PN结二极管
公开(公告)号：US09406661B2
公开(公告)日：2016-08-02
申请号：US14632352
申请日：2015-02-26
申请人： Alpha and Omega Semiconductor Incorporated
发明人： TingGang Zhu , Anup Bhalla , Ping Huang , Yueh-Se Ho
IPC分类号： H01L25/18 , H01L29/66 , H01L29/872 , H01L29/861 , H01L29/20 , H01L29/40 , H01L23/00
CPC分类号： H01L29/872 , H01L21/0217 , H01L21/0254 , H01L21/28581 , H01L21/30612 , H01L21/31111 , H01L21/56 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L25/18 , H01L27/0248 , H01L27/0814 , H01L29/0619 , H01L29/0688 , H01L29/2003 , H01L29/402 , H01L29/405 , H01L29/417 , H01L29/66136 , H01L29/66143 , H01L29/66212 , H01L29/861 , H01L29/8611 , H01L2224/0401 , H01L2224/04042 , H01L2224/05016 , H01L2224/05567 , H01L2224/11616 , H01L2224/13017 , H01L2224/13021 , H01L2224/13022 , H01L2924/00014 , H01L2924/1033 , H01L2924/12032 , H01L2924/12036 , H01L2924/12041 , H01L2924/12042 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
摘要： A circuit includes a vertical conduction gallium nitride-based Schottky diode and a vertical conduction silicon based PN junction diode connected in parallel. The Schottky diode and the PN junction diode are packaged in the same semiconductor package and the PN junction diode does not conduct in response to the Schottky diode being forward biased. In some embodiments, the silicon based PN junction diode has a breakdown voltage lower than a breakdown voltage of the gallium nitride-based Schottky diode. The silicon based PN junction diode enters breakdown in response to the gallium nitride-based Schottky diode being reverse biased to divert a reverse bias avalanche current away from the gallium nitride-based Schottky diode.
摘要翻译：电路包括并联连接的垂直导电氮化镓基肖特基二极管和垂直导电硅基PN结二极管。肖特基二极管和PN结二极管封装在相同的半导体封装中，并且PN结二极管不响应肖特基二极管正向偏置而导通。在一些实施例中，硅基PN结二极管的击穿电压低于基于氮化镓的肖特基二极管的击穿电压。基于硅的PN结二极管响应于反向偏置的氮化镓基肖特基二极管进入击穿，以将反向偏置雪崩电流转移离开基于氮化镓的肖特基二极管。

35. 发明授权

US09281394B2 Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact 有权
标题翻译：具有沟槽底部氧化物屏蔽和三维P体接触的纳米MOSFET
公开(公告)号：US09281394B2
公开(公告)日：2016-03-08
申请号：US14329751
申请日：2014-07-11
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Hamza Yilmaz , Daniel Ng , Daniel Calafut , Madhur Bobde , Anup Bhalla , Ji Pan , Yeeheng Lee , Jongoh Kim
IPC分类号： H01L29/78 , H01L29/66 , H01L29/10 , H01L21/265 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/06 , H01L29/08
CPC分类号： H01L29/7813 , H01L21/26586 , H01L27/088 , H01L29/0623 , H01L29/0626 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.
摘要翻译：半导体功率器件可以包括在重掺杂层上形成的轻掺杂层。在轻掺杂层中形成一个或多个器件。每个器件可以包括主体区域，源极区域和形成在轻掺杂区域中的对应沟槽中的一个或多个栅电极。每个沟槽具有第一维度的深度，第二维度中的宽度和第三维度中的长度。体区与轻掺杂层和重掺杂层具有相反的导电类型。源区域靠近上表面形成。在靠近一个或多个沟槽的第三维度的一个或多个位置处形成一个或多个深触点。触点在第一方向上从上表面延伸到轻掺杂层中并与源区电接触。

36. 发明授权

US09252264B2 High frequency switching MOSFETs with low output capacitance using a depletable P-shield 有权
公开(公告)号：US09252264B2
公开(公告)日：2016-02-02
申请号：US14566294
申请日：2014-12-10
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Madhur Bobde , Hamza Yilmaz , Sik Lui , Daniel Ng
IPC分类号： H01L29/76 , H01L29/78 , H01L27/04 , H01L29/66 , H01L29/06 , H01L29/10 , H01L27/02 , H01L29/40 , H01L29/47 , H01L21/225 , H01L29/417 , H01L29/423 , H01L29/45
CPC分类号： H01L29/7813 , H01L21/2257 , H01L27/0251 , H01L27/04 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/456 , H01L29/47 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7808 , H01L29/7811
摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

37. 发明申请

US20160005853A1 INTEGRATING SCHOTTKY DIODE INTO POWER MOSFET 有权
公开(公告)号：US20160005853A1
公开(公告)日：2016-01-07
申请号：US14318408
申请日：2014-06-27
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Yi Su , Daniel Ng , Anup Bhalla , Hong Chang , Jongoh Kim , John Chen
IPC分类号： H01L29/78 , H01L29/872 , H01L27/06 , H01L29/40 , H01L29/423
CPC分类号： H01L29/7801 , H01L21/26586 , H01L29/0623 , H01L29/0696 , H01L29/0891 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/47 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/78 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/782 , H01L29/872
摘要： A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

38. 发明授权

US09231050B1 Configuration and method to generate saddle junction electric field in edge termination 有权
公开(公告)号：US09231050B1
公开(公告)日：2016-01-05
申请号：US14298537
申请日：2014-06-06
申请人： Madhur Bobde , Lingping Guan , Anup Bhalla , Hamza Yilmaz
发明人： Madhur Bobde , Lingping Guan , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L27/088 , H01L29/06 , H01L21/761
CPC分类号： H01L29/0634 , H01L21/26513 , H01L21/761 , H01L29/0615 , H01L29/0619 , H01L29/6609 , H01L29/861
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

39. 发明授权

US09219003B2 Oxide terminated trench MOSFET with three or four masks 有权
公开(公告)号：US09219003B2
公开(公告)日：2015-12-22
申请号：US14606900
申请日：2015-01-27
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Sik Lui , Anup Bhalla
IPC分类号： H01L29/66 , H01L29/78 , H01L21/762 , H01L29/423 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/45
CPC分类号： H01L29/7813 , H01L21/3081 , H01L21/31 , H01L21/32133 , H01L21/76224 , H01L27/088 , H01L29/0638 , H01L29/0649 , H01L29/0653 , H01L29/0661 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/66666 , H01L29/66734 , H01L29/7811 , H01L29/7827
摘要： An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. Source and body regions inside the active region are at source potential and source and body regions outside the isolation trench are at drain potential. The device can be made using a three-mask or four-mask process.

40. 发明授权

US09214545B2 Dual gate oxide trench MOSFET with channel stop trench 有权
标题翻译：双栅极氧化沟槽MOSFET，具有通道停止沟槽
公开(公告)号：US09214545B2
公开(公告)日：2015-12-15
申请号：US14563974
申请日：2014-12-08
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Sung-Shan Tai , Sik Lui , Xiaobin Wang
IPC分类号： H01L29/66 , H01L21/336 , H01L29/78 , H01L29/40 , H01L29/06 , H01L29/08 , H01L29/417 , H01L29/423 , H01L29/45
CPC分类号： H01L29/7813 , H01L29/0638 , H01L29/0653 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device has a plurality of gate electrodes over a gate insulator layer formed in active trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the semiconductor substrate and electrically connected to the gate electrodes. The first gate runner abuts and surrounds the active region. A second gate runner is connected to the first gate runner to make contact to a gate metal. A dielectric filled trench surrounds the first and second gate runners and the active region and a highly doped channel stop region is formed under the dielectric filled trench.
摘要翻译：半导体器件在位于半导体衬底的有源区域的有源沟槽中形成的栅极绝缘体层上方具有多个栅电极。第一栅极流道形成在半导体衬底中并电连接到栅电极。第一个闸门赛跑者围绕活跃区域。第二浇口浇道连接到第一浇口浇道以与栅极金属接触。电介质填充的沟槽围绕第一和第二栅极流道和有源区，并且在电介质填充的沟槽下面形成高度掺杂的沟道阻挡区。

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