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31. 发明授权

US5930673A Method for forming a metal contact 失效
标题翻译：形成金属接触的方法
公开(公告)号：US5930673A
公开(公告)日：1999-07-27
申请号：US418122
申请日：1995-04-06
申请人： Fusen E. Chen , Fu-Tai Liou , Yih-Shung Lin , Girish A. Dixit , Che-Chia Wei
发明人： Fusen E. Chen , Fu-Tai Liou , Yih-Shung Lin , Girish A. Dixit , Che-Chia Wei
IPC分类号： H01L21/28 , C23C16/02 , C23C16/20 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/485 , H01L23/532 , H01L21/283
CPC分类号： H01L21/76843 , C23C16/0281 , C23C16/20 , H01L21/28512 , H01L21/32051 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L2924/0002
摘要： A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.
摘要翻译：提供了一种用于在半导体集成电路器件中沉积铝薄膜层以形成接触的方法。所有或一些沉积过程在允许改善沉积的铝原子的表面迁移的温度下以相对较低的沉积速率进行。在这些条件下沉积的铝倾向于填充接触孔而不形成空隙。低温沉积步骤可以通过沉积铝来开始，而包含集成电路器件的晶片正在从沉积室内的较冷的温度加热。

32. 发明授权

US5578872A Planar contact with a void 失效
标题翻译：与空虚平面接触
公开(公告)号：US5578872A
公开(公告)日：1996-11-26
申请号：US418838
申请日：1995-04-07
申请人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
发明人： Fusen E. Chen , Girish A. Dixit , Robert O. Miller
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L29/41 , H01L29/43
CPC分类号： H01L21/76843 , H01L21/76877 , Y10S257/915
摘要： A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A first conductive structure is formed over the integrated circuit. A dielectric is formed over the first conductive structure having a contact opening exposing a portion of the underlying first conductive layer. A barrier layer is formed in the bottom of the contact opening. A second, substantially conformal conductive layer is formed by chemical vapor deposition over the dielectric layer; along the sidewalls and in the bottom of the contact opening. A third conductive layer is then formed over the second conductive layer wherein the third conductive layer does not fill the contact opening. The second and third conductive layers are etched to form an interconnect substantially over the contact opening.
摘要翻译：提供了用于图案化集成电路的亚微米半导体层的方法，以及根据该集成电路形成的集成电路。在集成电路上形成第一导电结构。在第一导电结构上形成电介质，其具有暴露下面的第一导电层的一部分的接触开口。阻挡层形成在接触开口的底部。通过化学气相沉积在介电层上形成第二基本上保形的导电层; 沿着接触开口的侧壁和底部。然后在第二导电层上形成第三导电层，其中第三导电层不填充接触开口。第二和第三导电层被蚀刻以形成基本上在接触开口上的互连。

33. 发明授权

US5523624A Integrated circuit device structure with dielectric and metal stacked plug in contact hole 失效
标题翻译：集成电路器件结构，电介质和金属堆叠插头接触孔
公开(公告)号：US5523624A
公开(公告)日：1996-06-04
申请号：US112863
申请日：1993-08-26
申请人： Fusen E. Chen , Robert O. Miller , Girish A. Dixit
发明人： Fusen E. Chen , Robert O. Miller , Girish A. Dixit
IPC分类号： H01L21/28 , H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L29/417 , H01L29/43
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/76843 , H01L21/76844 , H01L21/76877 , Y10S257/915
摘要： A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A conductive structure is formed on the integrated circuit. A dielectric layer is formed over the integrated circuit. A contact opening is formed in the dielectric layer exposing a portion of the underlying first conductive structure. A barrier layer is formed on the dielectric layer and in the contact opening. A substantially conformal layer is formed over the barrier layer and in the contact opening. The conformal layer is partially etched away wherein the conformal layer remains only in a bottom portion of the contact opening. A second conductive layer is formed over the barrier layer and the remaining conformal layer.
摘要翻译：提供了用于图案化集成电路的亚微米半导体层的方法，以及根据该集成电路形成的集成电路。在集成电路上形成导体结构。在集成电路上形成介电层。在电介质层中形成接触开口，暴露下面的第一导电结构的一部分。在电介质层和接触开口中形成阻挡层。在阻挡层和接触开口中形成基本上共形的层。共形层被部分蚀刻掉，其中保形层仅保留在接触开口的底部。在阻挡层和剩余的保形层上形成第二导电层。

34. 发明授权

US5491355A Self-aligned contact formation 失效
标题翻译：自对准接触形成
公开(公告)号：US5491355A
公开(公告)日：1996-02-13
申请号：US97366
申请日：1993-07-23
申请人： Che C. Wei , Chiara Zaccherini , Robert O. Miller , Girish A. Dixit
发明人： Che C. Wei , Chiara Zaccherini , Robert O. Miller , Girish A. Dixit
IPC分类号： H01L21/74 , H01L21/768 , H01L23/485 , H01L29/45 , H01L29/04
CPC分类号： H01L21/76895 , H01L21/743 , H01L23/485 , H01L29/456 , H01L2924/0002
摘要： A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact opening to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.
摘要翻译：沉积并图案化多晶硅层以限定互连水平。然后对下导电层的接触开口被限定和图案化。诸如钨的难熔金属被选择性地沉积在器件上，使得其粘附到互连引线中的多晶硅和暴露在接触开口中的下导电层的硅。这提供了低电阻互连，以及良好的金属触点到底层。使用该技术容易地形成两个或更多个多晶硅互连层之间和底层导电层（例如基板）中的共用接触。

35. 发明授权

US5444019A Semiconductor contact via structure and method 失效
标题翻译：半导体接触通过结构和方法
公开(公告)号：US5444019A
公开(公告)日：1995-08-22
申请号：US157571
申请日：1993-11-24
申请人： Fusen E. Chen , Girish A. Dixit , Che-Chia Wei
发明人： Fusen E. Chen , Girish A. Dixit , Che-Chia Wei
IPC分类号： H01L21/28 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/70 , H01L27/00
CPC分类号： H01L23/5226 , H01L21/76801 , H01L21/76804 , H01L21/76814 , H01L21/76831 , H01L23/5329 , H01L23/53295 , H01L2924/0002
摘要： A method is provided for forming an integrated circuit contact structure. A conductive region is formed on a semiconductor device. Thereafter an insulating layer is formed over the conductive region. An opening is then formed through the insulating region to the conductive region. A thin barrier layer is deposited over the integrated circuit contact structure. A portion of the thin barrier layer is removed by backsputtering the integrated circuit contact structure so that only a thin barrier sidewall remains. Finally, a conductive metal layer is deposited over the integrated circuit contact structure. In one embodiment, the integrated circuit contact structure is baked before the conductive metal layer is deposited.
摘要翻译：提供了一种用于形成集成电路接触结构的方法。在半导体器件上形成导电区域。此后，在导电区域上形成绝缘层。然后通过绝缘区域形成到导电区域的开口。薄的势垒层沉积在集成电路接触结构上。通过反向溅射集成电路接触结构来去除薄势垒层的一部分，使得只有薄的阻挡侧壁保留。最后，在集成电路接触结构上沉积导电金属层。在一个实施例中，在沉积导电金属层之前烘烤集成电路接触结构。

36. 发明授权

US5369302A Method to improve step coverage by contact reflow 失效
标题翻译：通过接触回流改善步骤覆盖的方法
公开(公告)号：US5369302A
公开(公告)日：1994-11-29
申请号：US840679
申请日：1992-02-21
申请人： Fusen E. Chen , Girish A. Dixit
发明人： Fusen E. Chen , Girish A. Dixit
IPC分类号： H01L21/285 , H01L21/768 , H01L21/90
CPC分类号： H01L21/28518 , H01L21/76804 , H01L21/76877 , H01L21/76879
摘要： The method for fabrication of semiconductor contacts resulting in rounded contact corners providing for increased step coverage includes depositing a glass layer over a substrate and heating the glass layer to reflow. The glass layer is patterned and etched to form a contact opening. A barrier layer is deposited, annealed, and selectively wet etched leaving the barrier layer only in the bottom of the contact opening. The glass layer is reflowed again to form rounded contact corners.
摘要翻译：用于制造半导体触点的方法导致提供增加的阶梯覆盖的圆形接触角包括在基板上沉积玻璃层并加热玻璃层以回流。将玻璃层图案化并蚀刻以形成接触开口。阻挡层被沉积，退火并选择性地湿蚀刻，仅在接触开口的底部留下阻挡层。玻璃层再次回流以形成圆形接触角。

37. 发明授权

US5108951A Method for forming a metal contact 失效
标题翻译：形成金属接触的方法
公开(公告)号：US5108951A
公开(公告)日：1992-04-28
申请号：US609883
申请日：1990-11-05
申请人： Fusen E. Chen , Fu-Tai Liou , Yih-Shung Lin , Girish A. Dixit , Che-Chia Wei
发明人： Fusen E. Chen , Fu-Tai Liou , Yih-Shung Lin , Girish A. Dixit , Che-Chia Wei
IPC分类号： H01L21/28 , C23C16/02 , C23C16/20 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/485 , H01L23/532
CPC分类号： H01L21/76843 , C23C16/0281 , C23C16/20 , H01L21/28512 , H01L21/32051 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L2924/0002
摘要： A method is provided for depositing aluminum thin film layers to form improved quality contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.

38. 发明授权

US08858763B1 Apparatus and methods for deposition and/or etch selectivity 有权
标题翻译：用于沉积和/或蚀刻选择性的装置和方法
公开(公告)号：US08858763B1
公开(公告)日：2014-10-14
申请号：US12391719
申请日：2009-02-24
申请人： Erich R. Klawuhn , Robert Rozbicki , Girish A. Dixit
发明人： Erich R. Klawuhn , Robert Rozbicki , Girish A. Dixit
IPC分类号： C23C14/34
CPC分类号： C23C14/046 , C23C14/3407 , C23C14/345 , C23C14/3492 , C23C14/35 , H01J37/32596 , H01J37/3405 , H01L21/2855 , H01L21/32131 , H01L21/76805 , H01L21/76814 , H01L21/76844 , H01L21/76868
摘要： Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.
摘要翻译：公开了用于在半导体晶片的通路和沟槽中实现蚀刻和/或沉积选择性的装置和方法实施例。也就是说，半导体晶片的每个通孔的底部的沉积覆盖不同于这种晶片的每个沟槽的底部的覆盖。选择性可以被配置为导致每个通孔中的穿孔而不损坏每个沟槽等的底部处的电介质材料。在这种配置中，沉积在每个沟槽中的覆盖率大于沉积在每个通孔中的覆盖量。

39. 发明授权

US06869516B2 Method for removing electrolyte from electrical contacts and wafer touching areas 失效
标题翻译：从电触点和晶片接触区域去除电解质的方法
公开(公告)号：US06869516B2
公开(公告)日：2005-03-22
申请号：US10273539
申请日：2002-10-18
申请人： Dmitry Lubomirsky , Michael X. Yang , Girish A. Dixit , Vincent E. Burkhart , Allen L. D'Ambra , Yeuk-Fai Edwin Mok , Harald Herchen
发明人： Dmitry Lubomirsky , Michael X. Yang , Girish A. Dixit , Vincent E. Burkhart , Allen L. D'Ambra , Yeuk-Fai Edwin Mok , Harald Herchen
IPC分类号： C25D7/12 , C25D21/00 , H01L21/288 , C25D5/48
CPC分类号： C25D7/12 , C25D21/00 , H01L21/2885
摘要： A method for cleaning the electrical contact areas or substrate contact areas of an electrochemical plating contact ring is provided. Embodiments of the method include positioning a substrate on a substrate support member having one or more electrical contacts, chemically plating a metal layer on at least a portion of a surface of the substrate, removing the processed substrate from the support member, and cleaning the one or more electrical contacts with a vapor mixture comprising an alcohol. In another aspect, the method includes spraying the vapor mixture on the electrical contacts while rotating the substrate support member.
摘要翻译：提供了一种用于清洁电化学电镀接触环的电接触区域或衬底接触区域的方法。该方法的实施例包括将基板定位在具有一个或多个电触点的基板支撑构件上，在基板表面的至少一部分上化学镀覆金属层，从处理基板移除经处理的基板，并清洁该基板或更多的与包含醇的蒸汽混合物的电接触。在另一方面，该方法包括在旋转衬底支撑构件的同时将蒸气混合物喷射到电触点上。

40. 发明授权

US06297125B1 Air-bridge integration scheme for reducing interconnect delay 有权
标题翻译：降低互连延迟的气桥整合方案
公开(公告)号：US06297125B1
公开(公告)日：2001-10-02
申请号：US09233252
申请日：1999-01-19
申请人： Somnath S. Nag , Amitava Chatterjee , Girish A. Dixit
发明人： Somnath S. Nag , Amitava Chatterjee , Girish A. Dixit
IPC分类号： H01L2176
CPC分类号： H01L21/7682
摘要： Air-bridges are formed at controlled lateral separations using the extremely high HF etch rate of a gap-fill spin-on-glass such as uncured hydrogen silsequioxane (HSQ) in combination with other dielectrics having a much slower etch rate in HF. The advantages of an air-bridge system with controlled lateral separations include providing an interconnect isolation dielectric which meets all requirements for sub-0.5 micron technologies and providing a device with reduced reliability problems.
摘要翻译：使用间隙填充旋涂玻璃（例如未固化的氢硅氧烷（HSQ））的非常高的HF蚀刻速率与HF中具有慢得多的蚀刻速率的其它电介质组合，以可控的横向间隔形成空气桥。具有受控横向分离的空气桥系统的优点包括提供互补隔离电介质，其满足对于0.5微米以下技术的所有要求，并提供具有降低的可靠性问题的装置。

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