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31. 发明授权

US07685409B2 On-demand multi-thread multimedia processor 有权
标题翻译：按需多线程多媒体处理器
公开(公告)号：US07685409B2
公开(公告)日：2010-03-23
申请号：US11677362
申请日：2007-02-21
申请人： Yun Du , Guofang Jiao , Chun Yu
发明人： Yun Du , Guofang Jiao , Chun Yu
IPC分类号： G06F9/00
CPC分类号： G06F12/0842 , G06F9/30145 , G06F9/30167 , G06F9/382 , G06F9/383 , G06F9/3851 , G06F9/3885 , G06F9/45558 , G06F9/5016 , G06F12/10 , G06F2009/45579 , G06F2009/45583 , Y02D10/13 , Y02D10/22
摘要： A device includes a multimedia processor that can concurrently support multiple applications for various types of multimedia such as graphics, audio, video, camera, games, etc. The multimedia processor includes configurable storage resources to store instructions, data, and state information for the applications and assignable processing units to perform various types of processing for the applications. The configurable storage resources may include an instruction cache to store instructions for the applications, register banks to store data for the applications, context registers to store state information for threads of the applications, etc. The processing units may include an arithmetic logic unit (ALU) core, an elementary function core, a logic core, a texture sampler, a load control unit, a flow controller, etc. The multimedia processor allocates a configurable portion of the storage resources to each application and dynamically assigns the processing units to the applications as requested by these applications.
摘要翻译：一种设备包括多媒体处理器，其可以同时支持用于各种类型的多媒体（例如图形，音频，视频，照相机，游戏等）的多个应用。多媒体处理器包括可配置的存储资源以存储用于应用的指令，数据和状态信息以及可分配处理单元来执行用于应用的各种类型的处理。可配置的存储资源可以包括用于存储用于应用的指令的指令高速缓存，寄存器组存储用于应用的数据，上下文寄存器以存储用于应用的线程的状态信息等。处理单元可以包括算术逻辑单元（ALU ）核心，基本功能核心，逻辑核心，纹理采样器，负载控制单元，流量控制器等。多媒体处理器将存储资源的可配置部分分配给每个应用，并且将处理单元动态地分配给应用按照这些应用的要求。

32. 发明申请

US20090073168A1 FRAGMENT SHADER BYPASS IN A GRAPHICS PROCESSING UNIT, AND APPARATUS AND METHOD THEREOF 有权
标题翻译：图形处理单元中的片状阴影旁边，及其装置及方法
公开(公告)号：US20090073168A1
公开(公告)日：2009-03-19
申请号：US11855832
申请日：2007-09-14
申请人： Guofang Jiao , Yun Du , Chun Yu
发明人： Guofang Jiao , Yun Du , Chun Yu
IPC分类号： G06T15/50
CPC分类号： G06T15/005
摘要： Configuration information is used to make a determination to bypass fragment shading by a shader unit of a graphics processing unit, the shader unit capable of performing both vertex shading and fragment shader. Based on the determination, the shader unit performs vertex shading and bypasses fragment shading. A processing element other than the shader unit, such as a pixel blender, can be used to perform some fragment shading. Power is managed to “turn off” power to unused components in a case that fragment shading is bypassed. For example, power can be turned off to a number of arithmetic logic units, the shader unit using the reduced number of arithmetic logic unit to perform vertex shading. At least one register bank of the shader unit can be used as a FIFO buffer storing pixel attribute data for use, with texture data, to fragment shading operations by another processing element.
摘要翻译：配置信息用于确定通过图形处理单元的着色器单元绕过片段着色，着色器单元能够执行顶点着色和片段着色。基于确定，着色器单元执行顶点着色并绕过片段着色。可以使用除着色器单元之外的处理元件，例如像素混合器，以执行某些片段着色。在绕过片段着色的情况下，Power被设计为“关闭”未使用组件的电源。例如，功率可以关闭到多个算术逻辑单元，着色器单元使用减少数量的算术逻辑单元来执行顶点着色。着色器单元的至少一个寄存器组可以用作FIFO缓冲器，其存储与纹理数据一起使用的像素属性数据，以分割另一个处理元件的着色操作。

33. 发明申请

US20080059966A1 DEPENDENT INSTRUCTION THREAD SCHEDULING 有权
标题翻译：相关指令线程调度
公开(公告)号：US20080059966A1
公开(公告)日：2008-03-06
申请号：US11468221
申请日：2006-08-29
申请人： Yun Du , Guofang Jiao , Chun Yu
发明人： Yun Du , Guofang Jiao , Chun Yu
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3824 , G06F9/3838
摘要： A thread scheduler includes context units for managing the execution of threads where each context unit includes a load reference counter for maintaining a counter value indicative of a difference between a number of data requests and a number of data returns associated with the particular context unit. A context controller of the thread context unit is configured to refrain from forwarding an instruction of a thread when the counter value is nonzero and the instruction includes a data dependency indicator indicating the instruction requires data returned by a previous instruction.
摘要翻译：线程调度器包括用于管理线程执行的上下文单元，其中每个上下文单元包括负载参考计数器，用于维持指示多个数据请求与与特定上下文单元相关联的数据返回数量之间的差异的计数器值。线程上下文单元的上下文控制器被配置为当计数器值非零时避免转发线程的指令，并且该指令包括指示该指令需要先前指令返回的数据的数据依赖指示符。

34. 发明申请

US20080059756A1 RELATIVE ADDRESS GENERATION 有权
标题翻译：相对地址生成
公开(公告)号：US20080059756A1
公开(公告)日：2008-03-06
申请号：US11469347
申请日：2006-08-31
申请人： Yun Du , Chun Yu , Guofang Jiao
发明人： Yun Du , Chun Yu , Guofang Jiao
IPC分类号： G06F12/10
CPC分类号： G06F12/06 , G06F9/345 , G06F9/355 , G06F9/3802 , G06F9/3875
摘要： Techniques to efficiently handle relative addressing are described. In one design, a processor includes an address generator and a storage unit. The address generator receives a relative address comprised of a base address and an offset, obtains a base value for the base address, sums the base value with the offset, and provides an absolute address corresponding to the relative address. The storage unit receives the base address and provides the base value to the address generator. The storage unit also receives the absolute address and provides data at this address. The address generator may derive the absolute address in a first clock cycle of a memory access. The storage unit may provide the data in a second clock cycle of the memory access. The storage unit may have multiple (e.g., two) read ports to support concurrent address generation and data retrieval.
摘要翻译：描述了有效处理相对寻址的技术。在一种设计中，处理器包括地址发生器和存储单元。地址生成器接收由基地址和偏移组成的相对地址，获得基地址的基值，将基本值与偏移量相加，并提供与相对地址对应的绝对地址。存储单元接收基地址并将其提供给地址生成器。存储单元还接收绝对地址，并在该地址处提供数据。地址生成器可以在存储器访问的第一时钟周期中导出绝对地址。存储单元可以在存储器访问的第二时钟周期中提供数据。存储单元可以具有多个（例如两个）读端口，以支持并发地址生成和数据检索。

35. 发明申请

US20080030513A1 Graphics processing unit with extended vertex cache 有权
标题翻译：具有扩展顶点缓存的图形处理单元
公开(公告)号：US20080030513A1
公开(公告)日：2008-02-07
申请号：US11499187
申请日：2006-08-03
申请人： Guofang Jiao , Brian Evan Ruttenberg , Chun Yu , Yun Du
发明人： Guofang Jiao , Brian Evan Ruttenberg , Chun Yu , Yun Du
IPC分类号： G06T1/60
CPC分类号： G06T15/005
摘要： Techniques are described for processing computerized images with a graphics processing unit (GPU) using an extended vertex cache. The techniques include creating an extended vertex cache coupled to a GPU pipeline to reduce an amount of data passing through the GPU pipeline. The GPU pipeline receives an image geometry for an image, and stores attributes for vertices within the image geometry in the extended vertex cache. The GPU pipeline only passes vertex coordinates that identify the vertices and vertex cache index values that indicate storage locations of the attributes for each of the vertices in the extended vertex cache to other processing stages along the GPU pipeline. The techniques described herein defer the setup of attribute gradients to just before attribute interpolation in the GPU pipeline. The vertex attributes may be retrieved from the extended vertex cache for attribute gradient setup just before attribute interpolation in the GPU pipeline.
摘要翻译：描述了使用扩展顶点高速缓存处理具有图形处理单元（GPU）的计算机化图像的技术。这些技术包括创建一个连接到GPU流水线的扩展顶点缓存，以减少通过GPU流水线的数据量。 GPU流水线接收图像的图像几何，并在扩展顶点高速缓存中存储图像几何中的顶点的属性。 GPU流水线仅通过顶点坐标，其顶点和顶点高速缓存索引值指示扩展顶点高速缓存中每个顶点的属性的存储位置，沿着GPU流水线到其他处理阶段。本文描述的技术将属性梯度的设置延迟到GPU管线中的属性插值之前。可以从扩展顶点高速缓存中检索顶点属性，以便在GPU管线中的属性插值之前进行属性梯度设置。

36. 发明申请

US20080028152A1 Tiled cache for multiple software programs 有权
标题翻译：多个软件程序的平铺缓存
公开(公告)号：US20080028152A1
公开(公告)日：2008-01-31
申请号：US11493444
申请日：2006-07-25
申请人： Yun Du , Guofang Jiao , Chun Yu , De Dzwo Hsu
发明人： Yun Du , Guofang Jiao , Chun Yu , De Dzwo Hsu
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0864 , G06F9/3802 , G06F9/3851 , G06F12/0842
摘要： Caching techniques for storing instructions, constant values, and other types of data for multiple software programs are described. A cache provides storage for multiple programs and is partitioned into multiple tiles. Each tile is assignable to one program. Each program may be assigned any number of tiles based on the program's cache usage, the available tiles, and/or other factors. A cache controller identifies the tiles assigned to the programs and generates cache addresses for accessing the cache. The cache may be partitioned into physical tiles. The cache controller may assign logical tiles to the programs and may map the logical tiles to the physical tiles within the cache. The use of logical and physical tiles may simplify assignment and management of the tiles.
摘要翻译：描述用于存储用于多个软件程序的指令，常数值和其他类型的数据的缓存技术。高速缓存为多个程序提供存储，并分区成多个瓦片。每个瓦片可分配给一个程序。可以基于程序的高速缓存使用，可用的瓦片和/或其它因素来为每个程序分配任意数量的瓦片。缓存控制器识别分配给程序的块，并生成用于访问高速缓存的高速缓存地址。缓存可以被划分成物理块。高速缓存控制器可以向程序分配逻辑块，并且可以将逻辑块映射到高速缓存内的物理块。逻辑和物理瓦片的使用可以简化瓦片的分配和管理。

37. 发明授权

US08633936B2 Programmable streaming processor with mixed precision instruction execution 有权
标题翻译：具有混合精度指令执行的可编程流处理器
公开(公告)号：US08633936B2
公开(公告)日：2014-01-21
申请号：US12106654
申请日：2008-04-21
申请人： Yun Du , Chun Yu , Guofang Jiao , Stephen Molloy
发明人： Yun Du , Chun Yu , Guofang Jiao , Stephen Molloy
IPC分类号： G06T1/00 , G06F15/00 , G06F15/16
CPC分类号： G06T15/005 , G06F8/47
摘要： The disclosure relates to a programmable streaming processor that is capable of executing mixed-precision (e.g., full-precision, half-precision) instructions using different execution units. The various execution units are each capable of using graphics data to execute instructions at a particular precision level. An exemplary programmable shader processor includes a controller and multiple execution units. The controller is configured to receive an instruction for execution and to receive an indication of a data precision for execution of the instruction. The controller is also configured to receive a separate conversion instruction that, when executed, converts graphics data associated with the instruction to the indicated data precision. When operable, the controller selects one of the execution units based on the indicated data precision. The controller then causes the selected execution unit to execute the instruction with the indicated data precision using the graphics data associated with the instruction.
摘要翻译：本公开涉及一种能够使用不同执行单元执行混合精度（例如，全精度，半精度）指令的可编程流式处理器。各种执行单元都能够使用图形数据来执行特定精度级别的指令。示例性可编程着色器处理器包括控制器和多个执行单元。控制器被配置为接收用于执行的指令并且接收用于执行指令的数据精度的指示。控制器还被配置为接收单独的转换指令，该指令在执行时将与指令相关联的图形数据转换为所指示的数据精度。当可操作时，控制器基于指示的数据精度选择一个执行单元。然后，控制器使所选择的执行单元使用与指令相关联的图形数据，以指示的数据精度执行指令。

38. 发明授权

US08458497B2 Demand based power control in a graphics processing unit 有权
标题翻译：图形处理单元中基于需求的功率控制
公开(公告)号：US08458497B2
公开(公告)日：2013-06-04
申请号：US11870597
申请日：2007-10-11
申请人： Yun Du , Chun Yu , Guofang Jiao , Stephen Molloy
发明人： Yun Du , Chun Yu , Guofang Jiao , Stephen Molloy
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06T1/20
CPC分类号： G06F1/3203 , G06F1/3287 , G06T1/20 , Y02D10/171 , Y02D50/20
摘要： Disclosed herein is power controller for use with a graphics processing unit. The power controller monitors, manages and controls power supplied to components of a pipeline of the graphics processing unit. The power controller determining whether and to what extent power is to be supplied to a pipeline component based on status information received by the power controller in connection with the pipeline component. The power controller is capable of identifying a trend using the received status information, and determining whether and to what extent power is to be supplied to a pipeline component based on the identified trend.
摘要翻译：这里公开了与图形处理单元一起使用的功率控制器。功率控制器监视，管理和控制提供给图形处理单元的管线的组件的电力。功率控制器基于由电力控制器与流水线部件相关联的状态信息来确定是否以及在何种程度上向管道部件提供功率。功率控制器能够使用接收到的状态信息来识别趋势，并且基于所识别的趋势来确定是否以及在何种程度上向管道部件供电。

39. 发明授权

US08421794B2 Processor with adaptive multi-shader 有权
标题翻译：具有自适应多着色器的处理器
公开(公告)号：US08421794B2
公开(公告)日：2013-04-16
申请号：US11690358
申请日：2007-03-23
申请人： Yun Du , Guofang Jiao , Chun Yu
发明人： Yun Du , Guofang Jiao , Chun Yu
IPC分类号： G06T15/00 , G06F15/16 , G06F7/52 , G09G5/00
CPC分类号： G06T15/005
摘要： The disclosure describes an adaptive multi-shader within a processor that uses one or more high-precision arithmetic logic units (ALUs) and low-precision ALUs to process data based on the type of the data. Upon receiving a stream of data, the adaptive multi-shader first determines the type of the data. For example, the adaptive multi-shader may determine whether the data is suitable for high-precision processing or low-precision processing. The adaptive multi-shader then processes the data using the high-precision ALUs when the data is suitable for high-precision processing, and processes the data using the high-precision ALUs and the low-precision ALUs when the data is suitable for low-precision processing. The adaptive multi-shader may substantially reduce power consumption and silicon size of the processor by implementing the low-precision ALUs while maintaining the ability to process data using high-precision processing by implementing the high-precision ALUs.
摘要翻译：本公开描述了处理器内的自适应多着色器，其使用一个或多个高精度算术逻辑单元（ALU）和低精度ALU来基于数据的类型来处理数据。在接收到数据流之后，自适应多着色器首先确定数据的类型。例如，自适应多着色器可以确定数据是否适合于高精度处理或低精度处理。然后，当数据适用于高精度处理时，自适应多着色器使用高精度ALU处理数据，并且当数据适合低精度处理时，使用高精度ALU和低精度ALU处理数据，精密加工。自适应多着色器可以通过实施低精度ALU同时保持使用通过实施高精度ALU的高精度处理数据的能力来显着降低处理器的功耗和硅尺寸。

40. 发明授权

US08291431B2 Dependent instruction thread scheduling 有权
标题翻译：依赖指令线程调度
公开(公告)号：US08291431B2
公开(公告)日：2012-10-16
申请号：US11468221
申请日：2006-08-29
申请人： Yun Du , Guofang Jiao , Chun Yu
发明人： Yun Du , Guofang Jiao , Chun Yu
IPC分类号： G06F9/46 , G06F9/40
CPC分类号： G06F9/3851 , G06F9/3824 , G06F9/3838
摘要： A thread scheduler includes context units for managing the execution of threads where each context unit includes a load reference counter for maintaining a counter value indicative of a difference between a number of data requests and a number of data returns associated with the particular context unit. A context controller of the thread context unit is configured to refrain from forwarding an instruction of a thread when the counter value is nonzero and the instruction includes a data dependency indicator indicating the instruction requires data returned by a previous instruction.
摘要翻译：线程调度器包括用于管理线程执行的上下文单元，其中每个上下文单元包括负载参考计数器，用于维持指示多个数据请求与与特定上下文单元相关联的数据返回数量之间的差异的计数器值。线程上下文单元的上下文控制器被配置为当计数器值非零时避免转发线程的指令，并且该指令包括指示该指令需要先前指令返回的数据的数据依赖指示符。

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