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31. 发明授权

US4662949A Method of forming a single crystal semiconductor layer from a non-single crystalline material by a shaped energy beam 失效
标题翻译：通过成形能量束从非单晶材料形成单晶半导体层的方法
公开(公告)号：US4662949A
公开(公告)日：1987-05-05
申请号：US762374
申请日：1985-08-05
申请人： Tomoyasu Inoue , Hiroyuki Tango , Kyoichi Suguro , Iwao Higashinakagawa , Toshihiko Hamasaki
发明人： Tomoyasu Inoue , Hiroyuki Tango , Kyoichi Suguro , Iwao Higashinakagawa , Toshihiko Hamasaki
IPC分类号： H01L21/20 , H01L21/263 , H01L21/208
CPC分类号： H01L21/2636 , H01L21/2022 , Y10S148/093
摘要： In an apparatus for forming a single crystal semiconductor layer from a non-single-crystalline semiconductor material by scanning a region of the material with an electron beam, a first pair of deflection electrodes and a second pair of deflection electrodes, both pairs being provided in the path of the electron beam. A deflection signal generated by modifying the amplitude of a high-frequency fundamental wave signal with a modulation wave signal having a frequency lower than that of the high-frequency fundamental wave signal is supplied to the deflection electrodes of the first pair. The electrodes rapidly deflect the electron beam in a first direction, while changing the range of deflecting the beam, thereby forming a locus of the beam spot on the sample. Simultaneously, the deflection electrodes of the second pair deflect the beam in a second direction, thereby annealing a region of the material, to form a single crystal semiconductor layer.
摘要翻译：在通过用电子束扫描材料区域从非单晶半导体材料形成单晶半导体层的装置中，第一对偏转电极和第二对偏转电极设置在电子束的路径。通过用频率低于高频基波信号的调制波信号改变高频基波信号的振幅而产生的偏转信号被提供给第一对的偏转电极。电极在第一方向上快速偏转电子束，同时改变偏转光束的范围，从而在样品上形成束斑的轨迹。同时，第二对的偏转电极在第二方向上偏转光束，从而退火材料的区域，以形成单晶半导体层。

32. 发明授权

US08741161B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08741161B2
公开(公告)日：2014-06-03
申请号：US13428535
申请日：2012-03-23
申请人： Yasuyuki Sonoda , Kyoichi Suguro , Masatoshi Yoshikawa , Koji Yamakawa , Katsuaki Natori , Daisuke Ikeno
发明人： Yasuyuki Sonoda , Kyoichi Suguro , Masatoshi Yoshikawa , Koji Yamakawa , Katsuaki Natori , Daisuke Ikeno
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , H01L27/228 , H01L43/12
摘要： According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a pillar on a base layer, forming a insulating layer on the base layer to cover the pillar by using GCIB method, where a lowermost portion of an upper surface of the insulating layer is lower than an upper surface of the pillar, and polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method, where an end point of the polishing is the lowermost portion of the upper surface of the insulating layer.
摘要翻译：根据一个实施方案，一种制造半导体器件的方法，该方法包括在基底层上形成柱，在基底层上形成绝缘层以通过GCIB法覆盖柱，其中上表面的最下部分绝缘层低于柱的上表面，并且通过使用CMP方法研磨绝缘层和柱以露出柱的头部，其中抛光的终点是上表面的最下部绝缘层。

33. 发明申请

US20130069195A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130069195A1
公开(公告)日：2013-03-21
申请号：US13419882
申请日：2012-03-14
申请人： Kyoichi Suguro
发明人： Kyoichi Suguro
IPC分类号： H01L21/762 , H01L29/12
CPC分类号： H01L21/76254
摘要： According to one embodiment, a fabrication method for a semiconductor device includes: injecting an ion into a first substrate; joining the first substrate and a second substrate; irradiating a microwave to agglomerate the ion in a planar state in a desired position in the first substrate and form an agglomeration region spreading in a planar state; separating the second substrate provided with a part of the first substrate from the rest of the first substrate by exfoliating the joined first substrate from the second substrate in the agglomeration region; and grinding a part of the second substrate on a back surface opposite to an exfoliated surface in the second substrate provided with a part of the first substrate.
摘要翻译：根据一个实施例，一种用于半导体器件的制造方法包括：将离子注入第一衬底; 接合第一基板和第二基板; 照射微波以使平面状态的离子在第一基板中的期望位置聚集，并形成在平面状态下扩散的聚集区域; 通过将结合的第一基板从附聚区域中的第二基板剥离而将设置有第一基板的一部分的第二基板与第一基板的其余部分分离; 以及在设置有所述第一基板的一部分的所述第二基板中的与所述剥离表面相对的背面上研磨所述第二基板的一部分。

34. 发明授权

US08211785B2 Fabrication method for semiconductor device including flash lamp annealing processes 有权
标题翻译：包括闪光灯退火工艺的半导体器件的制造方法
公开(公告)号：US08211785B2
公开(公告)日：2012-07-03
申请号：US11819776
申请日：2007-06-29
申请人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
发明人： Takaharu Itani , Takayuki Ito , Kyoichi Suguro
IPC分类号： H01L21/425
CPC分类号： H01L21/26533 , H01L21/324 , H01L29/6659
摘要： A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion may be controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.
摘要翻译：通过退火形成具有注入离子的高激活速率，低电阻率和受控的漏电流的浅p-n结扩散层。通过光照射进行杂质掺杂后的退火。这些杂质通过在将杂质掺杂到半导体衬底11之后通过光照射退火至少两次来激活。光辐射的特征在于使用W卤素灯RTA或闪光灯FLA，除了使用闪光灯FLA的最终光照射。杂质扩散可以被控制到最小，并且当在源的源极和漏极延伸区域中形成离子注入层时，或者在源中的离子注入层形成离子注入层时，杂质掺杂过程中已经形成的晶体缺陷可以被充分地减小，以及漏极区域。

35. 发明授权

US07989903B2 Semiconductor device with extension structure and method for fabricating the same 有权
标题翻译：具有延伸结构的半导体器件及其制造方法
公开(公告)号：US07989903B2
公开(公告)日：2011-08-02
申请号：US12757658
申请日：2010-04-09
申请人： Takayuki Ito , Kyoichi Suguro , Kouji Matsuo
发明人： Takayuki Ito , Kyoichi Suguro , Kouji Matsuo
IPC分类号： H01L21/02
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823842
摘要： A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.
摘要翻译：半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。栅电极形成在第二栅绝缘膜上。

36. 发明申请

US20100055859A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100055859A1
公开(公告)日：2010-03-04
申请号：US12591085
申请日：2009-11-06
申请人： Takayuki Ito , Toshihiko Iinuma , Kyoichi Suguro
发明人： Takayuki Ito , Toshihiko Iinuma , Kyoichi Suguro
IPC分类号： H01L21/336 , H01L21/425
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2686 , H01L29/6653 , H01L29/66575 , H01L29/6659
摘要： Disclosed is a method for manufacturing a semiconductor device comprising implanting ions of an impurity element into a semiconductor region, implanting, into the semiconductor region, ions of a predetermined element which is a group IV element or an element having the same conductivity type as the impurity element and larger in mass number than the impurity element, and irradiating a region into which the impurity element and the predetermined element are implanted with light to anneal the region, the light having an emission intensity distribution, a maximum point of the distribution existing in a wavelength region of not more than 600 nm.
摘要翻译：公开了一种制造半导体器件的方法，包括将杂质元素的离子注入到半导体区域中，将作为IV族元素的预定元素或与杂质相同的导电类型的元素的离子注入半导体区域元素，并且质量数大于杂质元素，并且用光照射杂质元素和预定元素被注入的区域以使该区域退火，该光具有发光强度分布，存在于a的分布的最大点波长区域不大于600nm。

37. 发明申请

US20090206379A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090206379A1
公开(公告)日：2009-08-20
申请号：US12389266
申请日：2009-02-19
申请人： Soichirou Kitazaki , Hideaki Aochi , Kyoichi Suguro
发明人： Soichirou Kitazaki , Hideaki Aochi , Kyoichi Suguro
IPC分类号： H01L25/00 , H01L21/00 , H01L29/66 , H01L21/336
CPC分类号： H01L21/76831 , G11C11/22 , H01G4/1245 , H01G4/1254 , H01G4/33 , H01L21/31612 , H01L21/3162 , H01L21/31691 , H01L21/3185 , H01L23/485 , H01L23/5226 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L29/665 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device which can prevent the degradation of contact yield even when subjected to a high-temperature and long-time thermal process, and a manufacturing method thereof are provided. The semiconductor device includes: a first semiconductor circuit formed on a semiconductor substrate; a second semiconductor circuit formed above the first semiconductor circuit; an interlayer insulating film formed between the first semiconductor circuit and the second semiconductor circuit; and a contact plug formed in a state of penetrating the interlayer insulating film, the contact plug including a contact plug body made up of a conductor, and a contact plug coating which is insulating and which covers at least a portion of a side face of the contact plug body in contact with the interlayer insulating film.
摘要翻译：提供即使经受高温长时间热处理也能够防止接触性降低的半导体装置及其制造方法。半导体器件包括：形成在半导体衬底上的第一半导体电路; 形成在所述第一半导体电路之上的第二半导体电路; 形成在所述第一半导体电路和所述第二半导体电路之间的层间绝缘膜; 以及以穿透层间绝缘膜的状态形成的接触塞，所述接触插塞包括由导体构成的接触插塞体和绝缘的接触塞涂层，并且覆盖所述接触插塞的侧面的至少一部分接触插塞体与层间绝缘膜接触。

38. 发明授权

US07557040B2 Method of manufacture of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07557040B2
公开(公告)日：2009-07-07
申请号：US11644887
申请日：2006-12-26
申请人： Hiroshi Itokawa , Yoshimasa Kawase , Toshihiko Iinuma , Haruko Akutsu , Kyoichi Suguro
发明人： Hiroshi Itokawa , Yoshimasa Kawase , Toshihiko Iinuma , Haruko Akutsu , Kyoichi Suguro
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： A semiconductor device manufacturing method is disclosed. A silicon-containing gate electrode is first formed above the surface of a silicon-containing semiconductor substrate. Then, a sidewall insulating film is formed on the sidewall of the gate electrode and a film of metal is formed on the semiconductor substrate to cover the gate electrode and the sidewall insulating film. The front and back sides of the semiconductor substrate are heated through heat conduction by an ambient gas. Thereby, the metal is caused to react with silicon contained in the semiconductor substrate and the gate electrode to form a metal silicide film.
摘要翻译：公开了半导体器件制造方法。首先在含硅半导体衬底的表面上形成含硅栅电极。然后，在栅电极的侧壁上形成侧壁绝缘膜，并且在半导体衬底上形成金属膜以覆盖栅电极和侧壁绝缘膜。通过环境气体的热传导来加热半导体衬底的正面和背面。由此，使金属与包含在半导体衬底和栅电极中的硅反应，形成金属硅化物膜。

39. 发明授权

US07495293B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07495293B2
公开(公告)日：2009-02-24
申请号：US11512187
申请日：2006-08-30
申请人： Toshihiko Iinuma , Haruko Akutsu , Kyoichi Suguro
发明人： Toshihiko Iinuma , Haruko Akutsu , Kyoichi Suguro
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/495 , H01L29/4966 , H01L29/665 , H01L29/66795 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a silicon region including Si, and a silicide film provided on the silicon region, the silicide film comprising a compound of Si with Ni, Co, Pd, or Pt and including Er.
摘要翻译：半导体器件包括包含Si的硅区域和设置在硅区域上的硅化物膜，该硅化物膜包含Si与Ni，Co，Pd或Pt的化合物并包括Er的化合物。

40. 发明授权

US07144794B2 Ion source, ion implanting device, and manufacturing method of semiconductor devices 失效
标题翻译：离子源，离子注入装置以及半导体装置的制造方法
公开(公告)号：US07144794B2
公开(公告)日：2006-12-05
申请号：US10969025
申请日：2004-10-21
申请人： Kyoichi Suguro
发明人： Kyoichi Suguro
IPC分类号： H01L21/425
CPC分类号： H01J27/14 , H01J37/08 , H01J2237/31701
摘要： This ion source includes a chamber having an internal wall surface and an external wall surface, and also includes a cathode, which is provided to be insulated from the chamber, capable of emitting thermal electrons into the chamber, and has a cathode cap protruding into the chamber from an external side of an opening part which is formed to pass through from the external wall surface to the internal wall surface of the chamber and a filament disposed inside the cathode cap, the cathode cap and/or the filament being an alloy containing tungsten (W) as a major component and a predetermined metal element as a minor component.
摘要翻译：该离子源包括具有内壁表面和外壁表面的室，并且还包括阴极，该阴极被提供以与室绝缘，能够将热电子发射到室中，并且具有突出到阴极盖中的阴极帽腔室，其从形成为从外壁表面通过的开口部分的外侧延伸到腔室的内壁表面;以及细丝，其设置在阴极帽内部，阴极帽和/或细丝为含有钨的合金（W）作为主要成分，预定的金属元素作为次要成分。

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