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31. 发明授权

US07584327B2 Method and system for proximity caching in a multiple-core system 有权
标题翻译：多核系统中接近缓存的方法和系统
公开(公告)号：US07584327B2
公开(公告)日：2009-09-01
申请号：US11320788
申请日：2005-12-30
申请人： Yen-Kuang Chen , Christopher J. Hughes
发明人： Yen-Kuang Chen , Christopher J. Hughes
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/084 , Y02D10/13
摘要： Embodiments of the invention relate to a method and system for caching data in a multiple-core system with shared cache. According to the embodiments, data used by the cores may be classified as being of one of predetermined types. The classification may enable efficiencies to be realized by performing different types of handling corresponding to different data types. For example, data classified as likely to be re-used may be stored in a shared cache, in a region of the shared cache that is closest to a core using the data. By storing the data this way, access time and energy consumption may be reduced if the data is subsequently retrieved for use by the core.
摘要翻译：本发明的实施例涉及一种用于在具有共享高速缓存的多核系统中缓存数据的方法和系统。根据实施例，由核心使用的数据可以被分类为预定类型之一。该分类可以通过执行与不同数据类型相对应的不同类型的处理来实现效率。例如，分类为可能被重新使用的数据可以被存储在使用数据最接近核心的共享高速缓存的区域中的共享高速缓存中。通过以这种方式存储数据，如果数据随后被检索以供核心使用，则可以减少访问时间和能量消耗。

32. 发明申请

US20080022049A1 Dynamically re-classifying data in a shared cache 有权
标题翻译：在共享缓存中动态重新分类数据
公开(公告)号：US20080022049A1
公开(公告)日：2008-01-24
申请号：US11491043
申请日：2006-07-21
申请人： Christopher J. Hughes , Yen-Kuang Chen
发明人： Christopher J. Hughes , Yen-Kuang Chen
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , Y02D10/13
摘要： In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of a shared cache associated with a first requester unit based on the re-classification. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定数据状态是否指示第一类数据的方法，基于该确定将数据从第二类重新分类为第一类，并将数据移动到基于重新分类，与第一请求者单元相关联的共享缓存的第一部分。描述和要求保护其他实施例。

33. 发明授权

US07298782B2 Method and apparatus for improved memory management of video images 有权
标题翻译：用于改善视频图像的存储器管理的方法和装置
公开(公告)号：US07298782B2
公开(公告)日：2007-11-20
申请号：US10355704
申请日：2003-01-31
申请人： Valery Kuriakin , Alexander Knyazev , Roman Belenov , Yen-Kuang Chen
发明人： Valery Kuriakin , Alexander Knyazev , Roman Belenov , Yen-Kuang Chen
IPC分类号： H04N7/12
CPC分类号： H04N19/186 , G06T2200/28 , G09G5/42 , G09G2320/0261 , H04N19/423 , H04N19/433 , H04N19/44 , H04N19/61
摘要： A novel storage format enabling a method for improved memory management of video images is described. The method includes receiving an image consisting of a plurality of color components. Once received, the plurality of color components is converted to a mixed format of planar format and packed format. The mixed packet format is implemented by storing one or more of the plurality of color components in a planar format and storing one or more of the plurality of color components in a packed format. A method for writing out video images is also described utilizing a write combining (WC) fame buffer. The decoding method motion compensates groups of macroblocks in order to eliminate partial writes from the WC frame buffer.
摘要翻译：描述了一种使得能够改进视频图像的存储器管理的方法的新型存储格式。该方法包括接收由多个颜色分量组成的图像。一旦接收到，多个颜色分量被转换成平面格式和打包格式的混合格式。混合分组格式通过以平面格式存储多个颜色分量中的一个或多个并且以打包格式存储多个颜色分量中的一个或多个来实现。还使用写入组合（WC）名声缓冲器来描述用于写入视频图像的方法。解码方法运动补偿宏块组，以便消除来自WC帧缓冲器的部分写入。

34. 发明申请

US20070143759A1 Scheduling and partitioning tasks via architecture-aware feedback information 审中-公开
标题翻译：通过架构感知反馈信息调度和分区任务
公开(公告)号：US20070143759A1
公开(公告)日：2007-06-21
申请号：US11300809
申请日：2005-12-15
申请人： Aysel Ozgur , Gregory Buehrer , Anthony Nguyen , Daehyun Kim , Victor Lee , Mikhail Smelyanskiy , Yen-Kuang Chen
发明人： Aysel Ozgur , Gregory Buehrer , Anthony Nguyen , Daehyun Kim , Victor Lee , Mikhail Smelyanskiy , Yen-Kuang Chen
IPC分类号： G06F9/46
CPC分类号： G06F9/5066 , G06F9/5033
摘要： In one embodiment, the present invention includes a method for performing a first level task of an application in a first processor of a system and dynamically allocating a second level task of the application to one of the first processor and a second processor based on architectural feedback information. In this manner, improved scheduling and application performance can be achieved by better utilizing system resources. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在系统的第一处理器中执行应用的第一级任务的方法，并且基于架构反馈将应用的第二级任务动态地分配给第一处理器和第二处理器之一信息。以这种方式，可以通过更好地利用系统资源来实现改进的调度和应用性能。描述和要求保护其他实施例。

35. 发明授权

US07042942B2 Zigzag in-order for image/video encoder and decoder 失效
公开(公告)号：US07042942B2
公开(公告)日：2006-05-09
申请号：US10028402
申请日：2001-12-21
申请人： Yen-Kuang Chen , Wen-Hsiao Peng
发明人： Yen-Kuang Chen , Wen-Hsiao Peng
IPC分类号： H04B1/66 , H04N11/02 , H04N11/04 , H04N7/12
CPC分类号： H04N19/37 , H04N19/60
摘要： In an encoding or decoding process for compressible data, non-raster ordered bitstreams of transform data are rearranged in memory so later data access is contiguous, efficiently allowing processing in a single cache line. In an encoder, rearrangement can utilize a buffer copy that enables address calculation to performed only once per block.

36. 发明授权

US06957317B2 Apparatus and method for facilitating memory data access with generic read/write patterns 失效
标题翻译：用于利用通用读/写模式促进存储器数据访问的装置和方法
公开(公告)号：US06957317B2
公开(公告)日：2005-10-18
申请号：US10268186
申请日：2002-10-10
申请人： Yen-Kuang Chen , Eric Debes , Matthew J. Holliman , Minerva M. Yeung
发明人： Yen-Kuang Chen , Eric Debes , Matthew J. Holliman , Minerva M. Yeung
IPC分类号： G06F12/08 , G06T1/60 , G06T9/00 , G09G5/393 , G06F12/00
CPC分类号： G06F12/0875 , G06F12/0877 , G06T1/60 , G06T9/00 , G09G5/393 , G09G2360/121
摘要： An apparatus and method facilitating memory data access with generic read/write patterns are described. In one embodiment, the method includes the detection, in response to a load instruction, of a cache hit/cache miss of data requested by the load instruction within a re-tiling (RT) cache. When a cache miss is detected, a block of data is loaded into the RT cache according to the load instruction. This block of data will contain the data requested by the load instruction. Once loaded, a non-horizontally sequential access of the data requested by the load instruction is performed from the RT cache. Finally, the data accessed from the RT cache may be stored into a destination data storage device according to the load instruction.
摘要翻译：描述了利用通用读/写模式促进存储器数据访问的装置和方法。在一个实施例中，该方法包括响应于加载指令，检测在重新平铺（RT）高速缓存内由加载指令请求的数据的高速缓存命中/高速缓存未命中。当检测到高速缓存未命中时，根据加载指令将一块数据加载到RT缓存中。该数据块将包含加载指令请求的数据。一旦加载，从RT缓存执行加载指令请求的数据的非水平顺序访问。最后，从RT缓存访问的数据可以根据加载指令存储到目的地数据存储装置中。

37. 发明授权

US09513905B2 Vector instructions to enable efficient synchronization and parallel reduction operations 有权
公开(公告)号：US09513905B2
公开(公告)日：2016-12-06
申请号：US12079774
申请日：2008-03-28
申请人： Mikhail Smelyanskiy , Sanjeev Kumar , Daehyun Kim , Jatin Chhugani , Changkyu Kim , Christopher J. Hughes , Victor W. Lee , Anthony D. Nguyen , Yen-Kuang Chen
发明人： Mikhail Smelyanskiy , Sanjeev Kumar , Daehyun Kim , Jatin Chhugani , Changkyu Kim , Christopher J. Hughes , Victor W. Lee , Anthony D. Nguyen , Yen-Kuang Chen
IPC分类号： G06F15/80 , G06F9/40 , G06K9/00 , G06F9/30 , G06F9/38 , G06T5/40 , H04N1/407 , G06K9/62
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/3885 , G06K9/6212 , G06T5/40 , H04N1/4074
摘要： In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.

38. 发明授权

US08972698B2 Vector conflict instructions 有权
标题翻译：向量冲突指令
公开(公告)号：US08972698B2
公开(公告)日：2015-03-03
申请号：US12976616
申请日：2010-12-22
申请人： Christopher J. Hughes , Mark J. Charney , Yen-Kuang Chen , Jesus Corbal , Andrew T. Forsyth , Milind B. Girkar , Jonathan C. Hall , Hideki Ido , Robert Valentine , Jeffrey Wiedemeier
发明人： Christopher J. Hughes , Mark J. Charney , Yen-Kuang Chen , Jesus Corbal , Andrew T. Forsyth , Milind B. Girkar , Jonathan C. Hall , Hideki Ido , Robert Valentine , Jeffrey Wiedemeier
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30043 , G06F9/3838
摘要： A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.
摘要翻译：描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。

39. 发明授权

US08719500B2 Technique for tracking shared data in a multi-core processor or multi-processor system 有权
标题翻译：用于跟踪多核处理器或多处理器系统中的共享数据的技术
公开(公告)号：US08719500B2
公开(公告)日：2014-05-06
申请号：US12592998
申请日：2009-12-07
申请人： Yen-Kuang Chen , Christopher J. Hughes , Changkyn Kim
发明人： Yen-Kuang Chen , Christopher J. Hughes , Changkyn Kim
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： A technique to track shared information in a multi-core processor or multi-processor system. In one embodiment, core identification information (“core IDs”) are used to track shared information among multiple cores in a multi-core processor or multiple processors in a multi-processor system.
摘要翻译：一种在多核处理器或多处理器系统中跟踪共享信息的技术。在一个实施例中，核心识别信息（“核心ID”）用于在多处理器系统中的多核处理器或多个处理器中的多个核之间跟踪共享信息。

40. 发明授权

US08578097B2 Scatter-gather intelligent memory architecture for unstructured streaming data on multiprocessor systems 有权
公开(公告)号：US08578097B2
公开(公告)日：2013-11-05
申请号：US13280117
申请日：2011-10-24
申请人： Daehyun Kim , Christopher J. Hughes , Yen-Kuang Chen , Partha Kundu
发明人： Daehyun Kim , Christopher J. Hughes , Yen-Kuang Chen , Partha Kundu
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F12/08 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0862 , G06F12/0877 , G06F12/0891 , G06F12/0897 , G06F2212/6026 , G06F2212/62 , G11C7/1072 , G11C7/1075 , Y02D10/13
摘要： A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

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