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31. 发明授权

US07782646B2 High density content addressable memory using phase change devices 有权
标题翻译：使用相变装置的高密度内容寻址存储器
公开(公告)号：US07782646B2
公开(公告)日：2010-08-24
申请号：US12165530
申请日：2008-06-30
申请人： Chung Hon Lam , Bipin Rajendran
发明人： Chung Hon Lam , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C15/02 , G11C11/16 , G11C13/0004 , G11C15/04 , G11C15/046
摘要： A content addressable memory array storing stored words in memory elements. Each memory element stores one of at least two complementary binary bits as one of at least two complementary resistances. Each memory element is electrically coupled to an access device. An aspect of the content addressable memory array is the use of a biasing circuit to bias the access devices during a search operation. During the search operation, a search word containing a bit string is received. Each access device is biased to a complementary resistance value of a corresponding search bit in the search word. A match between the search word and stored word is indicated if the bits stored in the memory elements are complementary to the bits represented by the resistances in the access devices.
摘要翻译：一种在存储元件中存储存储字的内容可寻址存储器阵列。每个存储器元件将至少两个互补二进制位中的一个存储为至少两个互补电阻之一。每个存储器元件电耦合到访问设备。内容可寻址存储器阵列的一个方面是使用偏置电路来在搜索操作期间偏置访问设备。在搜索操作期间，接收包含位串的搜索词。每个访问设备被偏置到搜索词中相应搜索位的互补电阻值。如果存储在存储器元件中的位与由访问设备中的电阻表示的位互补，则指示搜索字和存储字之间的匹配。

32. 发明授权

US07965537B2 Phase change memory with finite annular conductive path 有权
标题翻译：具有有限环形导电路径的相变存储器
公开(公告)号：US07965537B2
公开(公告)日：2011-06-21
申请号：US12491816
申请日：2009-06-25
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/16 , Y10T29/49002
摘要： A phase change memory device and a method for programming the same. The method includes determining a maximum possible resistance for the memory cells in the phase change memory device. The method includes determining a high resistance state for the memory cells in the phase change memory device. The method includes receiving a request to program a target memory cell in the phase change memory device to the high resistance state. The method also includes resetting the target memory cell in the phase change memory device to the high resistance state such that the high resistance state of the target memory cell is of less resistance than the maximum possible resistance. In one embodiment of the invention, the high resistance state for the memory cells in the phase change memory device is at least 10% less than the maximum possible resistance.
摘要翻译：相变存储器件及其编程方法。该方法包括确定相变存储器件中的存储器单元的最大可能电阻。该方法包括确定相变存储器件中存储单元的高电阻状态。该方法包括接收将相变存储器件中的目标存储单元编程为高电阻状态的请求。该方法还包括将相变存储器件中的目标存储单元重置为高电阻状态，使得目标存储单元的高电阻状态的阻抗比最大可能的电阻小。在本发明的一个实施例中，相变存储器件中的存储单元的高电阻状态比最大可能电阻小至少10％。

33. 发明申请

US20110134676A1 RESISTIVE MEMORY DEVICES HAVING A NOT-AND (NAND) STRUCTURE 有权
标题翻译：具有非和（非）结构的电阻式存储器件
公开(公告)号：US20110134676A1
公开(公告)日：2011-06-09
申请号：US12631310
申请日：2009-12-04
申请人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
发明人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00 , G11C11/00 , G11C7/00
CPC分类号： G11C15/046 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C16/0483 , G11C2013/0088 , G11C2013/0092 , G11C2213/75
摘要： Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.
摘要翻译：具有包括电阻存储单元的非 - 和（NAND）结构的电阻存储器。电阻性存储单元包括用于存储电阻值的电阻性存储器元件和用于控制对电阻式存储器元件的访问的存储元件访问器件。存储元件存取装置与电阻式存储元件并联连接。

34. 发明申请

US20110116307A1 PHASE CHANGE MEMORY DEVICE SUITABLE FOR HIGH TEMPERATURE OPERATION 有权
标题翻译：相变式存储器件，适用于高温操作
公开(公告)号：US20110116307A1
公开(公告)日：2011-05-19
申请号：US12619362
申请日：2009-11-16
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran , Simone Raoux , Alejandro G. Schrott , Daniel Krebs
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran , Simone Raoux , Alejandro G. Schrott , Daniel Krebs
IPC分类号： H01L45/00 , G11C11/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0069 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A phase change memory cell that includes a bottom electrode, a top electrode separated from the bottom electrode, and growth-dominated phase change material deposited between the bottom electrode and the top electrode and contacting the bottom electrode and the top electrode and surrounded by insulation material at sidewalls thereof. The phase change memory cell in a reset state only includes an amorphous phase of the growth-dominated phase change material within an active volume of the phase change memory cell.
摘要翻译：一种相变存储单元，包括底部电极，从底部电极分离的顶部电极和沉积在底部电极和顶部电极之间的生长主导的相变材料，并且与底部电极和顶部电极接触并被绝缘材料包围在其侧壁。处于复位状态的相变存储单元仅包括在相变存储单元的有效体积内的以生长为主的相变材料的非晶相。

35. 发明授权

US07764533B2 Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition 有权
标题翻译：利用测量时间延迟作为电平定义的特征参数的多电平存储单元
公开(公告)号：US07764533B2
公开(公告)日：2010-07-27
申请号：US11857321
申请日：2007-09-18
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0061 , G11C11/5628 , G11C11/565 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C16/32 , G11C2013/0054
摘要： A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.
摘要翻译：用于操作存储器单元和存储器阵列的存储器阵列和计算机程序产品。本发明的实施例需要接收读取存储在存储单元中的二进制值的请求。预充电操作将由存储器单元形成的电子电路中的位线电容器预先充电到预充电电压。然后激活电子电路中的字线。放电操作通过电子电路中的所述存储单元将位线电容器放电到字线。此外，当字线被激活时，电子放电时间测量开始。当位线中的电压电平低于预定义的参考电压时，停止电子放电时间测量。确定操作根据测量的电子放电时间确定二进制值。

36. 发明授权

US07811879B2 Process for PCM integration with poly-emitter BJT as access device 有权
标题翻译：与多发射器BJT作为接入设备的PCM集成过程
公开(公告)号：US07811879B2
公开(公告)日：2010-10-12
申请号：US12121875
申请日：2008-05-16
申请人： Chung Hon Lam , Bipin Rajendran
发明人： Chung Hon Lam , Bipin Rajendran
IPC分类号： H01L21/8249
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/101
摘要： Techniques for forming a memory cell. An aspect of the invention includes forming FET gate stacks and sacrificial cell gate stacks over the substrate. Spacer layers are then formed around the FET gate stacks and around the sacrificial cell gate stacks. The sacrificial cell gate stacks are then removed such that the spacer layers around the sacrificial cell gate stacks are still intact. BJT cell stacks are then formed in the space between the spacer layers where the sacrificial cell gate stacks were formed and removed, the BJT cell stacks including an emitter layer. A phase change layer above the emitter contacts and an electrode above the phase change layer are then formed.
摘要翻译：形成记忆体的技术。本发明的一个方面包括在衬底上形成FET栅极叠层和牺牲电池栅叠层。然后在FET栅极堆叠周围以及牺牲电池栅极堆叠周围形成间隔层。然后去除牺牲单元栅极堆叠，使得牺牲单元栅极堆叠周围的间隔层仍然完整。 BJT电池堆随后形成在形成和去除牺牲电池栅极堆叠的间隔层之间的空间中，BJT电池堆包括发射极层。然后形成发射极上方的相变层和相变层上方的电极。

37. 发明授权

US08138574B2 PCM with poly-emitter BJT access devices 有权
标题翻译： PCM与多发射器BJT接入设备
公开(公告)号：US08138574B2
公开(公告)日：2012-03-20
申请号：US12510588
申请日：2009-07-28
申请人： Tze-Chiang Chen , Chung Hon Lam , Bipin Rajendran
发明人： Tze-Chiang Chen , Chung Hon Lam , Bipin Rajendran
IPC分类号： H01L27/06
CPC分类号： H01L45/1233 , H01L27/2445 , H01L27/2463 , H01L45/06
摘要： A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. A memory cell for a phase change memory (PCM) includes a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor.
摘要翻译：相变存储器（PCM）包括包括多个存储器单元的阵列，包括相变元件（PCE）的存储单元; 以及包括双极结型晶体管（BJT）的PCE存取装置，所述BJT包括包含多晶半导体的发射极区域。用于相变存储器（PCM）的存储单元包括相变元件（PCE）; 以及包括双极结型晶体管（BJT）的PCE存取装置，所述BJT包括包含多晶半导体的发射极区域。

38. 发明授权

US08648326B2 Phase change memory electrode with sheath for reduced programming current 有权
标题翻译：具有护套的相变记忆电极，用于减少编程电流
公开(公告)号：US08648326B2
公开(公告)日：2014-02-11
申请号：US13191490
申请日：2011-07-27
申请人： Matthew J. Breitwisch , Bipin Rajendran
发明人： Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/16
摘要： An example embodiment is a phase change memory cell that includes a bottom contact and an electrically insulating layer disposed over the bottom contact. The electrically insulating layer defines an elongated via. Furthermore, a bottom electrode is disposed at least partially in the via. The bottom electrode includes a sleeve of a first electrically conductive material surrounding a rod of a second electrically conductive material. The first electrically conductive material and the second electrically conductive material have different specific electrical resistances. The memory cell also includes a phase change layer electrically coupled to the first electrode.
摘要翻译：示例性实施例是相位存储单元，其包括底部触点和设置在底部触点上方的电绝缘层。电绝缘层限定细长的通孔。此外，底部电极至少部分地设置在通路中。底部电极包括围绕第二导电材料的杆的第一导电材料的套筒。第一导电材料和第二导电材料具有不同的比电阻。存储单元还包括电耦合到第一电极的相变层。

39. 发明申请

US20130026436A1 PHASE CHANGE MEMORY ELECTRODE WITH SHEATH FOR REDUCED PROGRAMMING CURRENT 有权
标题翻译：相位改变记忆电极，减少编程电流
公开(公告)号：US20130026436A1
公开(公告)日：2013-01-31
申请号：US13191490
申请日：2011-07-27
申请人： Matthew J. Breitwisch , Bipin Rajendran
发明人： Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： H01L47/00 , H01L21/20
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/16
摘要： An example embodiment is a phase change memory cell that includes a bottom contact and an electrically insulating layer disposed over the bottom contact. The electrically insulating layer defines an elongated via. Furthermore, a bottom electrode is disposed at least partially in the via. The bottom electrode includes a sleeve of a first electrically conductive material surrounding a rod of a second electrically conductive material. The first electrically conductive material and the second electrically conductive material have different specific electrical resistances. The memory cell also includes a phase change layer electrically coupled to the first electrode.
摘要翻译：示例性实施例是相位存储单元，其包括底部触点和设置在底部触点上方的电绝缘层。电绝缘层限定细长的通孔。此外，底部电极至少部分地设置在通路中。底部电极包括围绕第二导电材料的杆的第一导电材料的套筒。第一导电材料和第二导电材料具有不同的比电阻。存储单元还包括电耦合到第一电极的相变层。

40. 发明授权

US08233317B2 Phase change memory device suitable for high temperature operation 有权
标题翻译：相变存储器件适用于高温操作
公开(公告)号：US08233317B2
公开(公告)日：2012-07-31
申请号：US12619362
申请日：2009-11-16
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran , Simone Raoux , Alejandro G. Schrott , Daniel Krebs
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran , Simone Raoux , Alejandro G. Schrott , Daniel Krebs
IPC分类号： G11C11/00 , H01L47/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0069 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A phase change memory cell that includes a bottom electrode, a top electrode separated from the bottom electrode, and growth-dominated phase change material deposited between the bottom electrode and the top electrode and contacting the bottom electrode and the top electrode and surrounded by insulation material at sidewalls thereof. The phase change memory cell in a reset state only includes an amorphous phase of the growth-dominated phase change material within an active volume of the phase change memory cell.
摘要翻译：一种相变存储单元，包括底部电极，从底部电极分离的顶部电极和沉积在底部电极和顶部电极之间的生长主导的相变材料，并且与底部电极和顶部电极接触并被绝缘材料包围在其侧壁。处于复位状态的相变存储单元仅包括在相变存储单元的有效体积内的以生长为主的相变材料的非晶相。

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