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31. 发明授权

US06452844B2 Semiconductor storage device having redundancy circuit for replacement of defect cells under tests 有权
标题翻译：具有冗余电路的半导体存储装置，用于更换被测试的缺陷单元
公开(公告)号：US06452844B2
公开(公告)日：2002-09-17
申请号：US09739490
申请日：2000-12-18
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C700
CPC分类号： G11C29/72 , G11C29/40
摘要： A semiconductor storage device such as a DRAM is configured to enable testing on defectiveness of memory cells by an existing memory tester, which locates defect cells to be replaced with redundancy cells by a redundancy circuit. Herein, a write circuit writes multiple-bit data to memory cells of a memory cell array under testing. Then, the multiple-bit data are read from the memory cell array by a read circuit and are compared with original one to make decisions of “pass” or “fail” on the memory cells by the memory tester. Specifically, the read circuit is configured by plural pairs of a data output circuit and a data compression circuit with respect to plural sets of prescribed data each of which consists of a prescribed number of bits corresponding to prescribed memory cells which are subjected to simultaneous replacement. The data compression circuit is configured by an exclusive-or circuit that compresses a certain type of the prescribed data to specific data having a specific logical value. Or, the data compression circuit is configured using two exclusive-or circuits that compress different types of the prescribed data to specific data. The specific data is forwarded as single-bit data, based on which the memory tester makes decisions of “pass” or “fail” on the memory cells corresponding to bits of the prescribed data being read out.
摘要翻译：诸如DRAM的半导体存储装置被配置为能够通过现有存储器测试器对存储器单元的缺陷进行测试，该存储器测试器通过冗余电路定位要被冗余单元替换的缺陷单元。这里，写入电路将多位数据写入被测试的存储单元阵列的存储单元。然后，通过读取电路从存储单元阵列中读取多位数据，并将其与原始数据进行比较，以通过存储器测试器对存储器单元进行“通过”或“失败”判定。具体地，读取电路由多对数据输出电路和数据压缩电路构成，该数据输出电路和数据压缩电路相对于多组规定数据构成，每组规定数据由对应于同时替换的规定存储器单元的规定数量的位组成。数据压缩电路由将特定类型的规定数据压缩到具有特定逻辑值的特定数据的异或电路配置。或者，数据压缩电路使用将不同类型的规定数据压缩到特定数据的两个专用或电路来配置。特定数据作为单位数据转发，基于此，存储器测试器对与读出的规定数据的位对应的存储单元进行“通过”或“失败”判定。

32. 发明授权

US06414887B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06414887B2
公开(公告)日：2002-07-02
申请号：US09846252
申请日：2001-05-02
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C700
CPC分类号： G11C29/84
摘要： A semiconductor memory device is designed to speed up the selection of a word line. The semiconductor memory device comprises a plurality of normal row decoders for decoding input row address data for specifying word lines when access is made to those of memory cells of a memory cell array which are other than a redundant row of memory cells, thereby selecting those word lines to which those memory cells that are other than the redundant row of memory cells are connected; a redundant row decoder for specifying that word line to which the redundant row of memory cells is connected when access is made to any memory cell which belongs to the redundant row; decision means for determining whether or not to select a memory cell belonging to the redundant row based on the input row address data and selecting the redundant row decoder when selecting the memory cell belonging to the redundant row; and control means for changing only those word lines which are connected to the normal row decoders from an active state to a standby state based on a decision output of the decision means when the decision means has determined to select a memory cell belonging to the redundant row when changing the word lines connected to the normal row decoders from a standby state to an active state.
摘要翻译：半导体存储器件被设计成加速字线的选择。半导体存储器件包括多个正常行解码器，用于当对与存储器单元的冗余行不同的存储单元阵列的存储单元进行访问时，用于解码用于指定字线的输入行地址数据，从而选择这些字与存储器单元的冗余行不同的那些存储单元被连接到的行; 冗余行解码器，用于当对属于所述冗余行的任何存储单元进行访问时，指定所述冗余行存储单元连接到的字线; 决定装置，用于基于所输入的行地址数据确定是否选择属于所述冗余行的存储单元，并且在选择属于所述冗余行的存储单元时选择所述冗余行解码器; 以及控制装置，用于当判定装置确定选择属于冗余行的存储单元时，根据判定装置的判定输出，仅将那些连接到正常行解码器的字线从活动状态改变为待机状态当将连接到正常行解码器的字线从待机状态改变为活动状态时。

33. 发明授权

US06385104B2 Semiconductor memory device having a test mode decision circuit 有权
标题翻译：具有测试模式决定电路的半导体存储器件
公开(公告)号：US06385104B2
公开(公告)日：2002-05-07
申请号：US09839504
申请日：2001-04-20
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C700
CPC分类号： G11C29/50
摘要： The semiconductor memory device according to the present invention comprises a memory cell array having a plurality of memory cells, a plurality of bit lines, a plurality of word lines, a row decoder which selects a prescribed word line in response to a row address and a control signal, a test mode decision circuit which generates a test signal by deciding that the device is in a test mode, a control signal generating circuit which brings the control signal to the activated state and keeps it there for a prescribed duration in response to an instruction signal, wherein the control signal generating circuit has a means for setting the change of the control signal to the inactivated state in response to the occurrence of the test signal sooner than in the normal operation.
摘要翻译：根据本发明的半导体存储器件包括具有多个存储单元的存储单元阵列，多个位线，多个字线，行解码器，其响应于行地址选择规定的字线，以及控制信号，通过判定设备处于测试模式来产生测试信号的测试模式判定电路，控制信号产生电路，其使控制信号处于激活状态，并响应于控制信号将其保持在规定的持续时间指令信号，其中所述控制信号发生电路具有用于响应于所述测试信号的发生比在所述正常操作中更早地将所述控制信号的改变设置为所述非激活状态的装置。

34. 发明授权

US06385095B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06385095B2
公开(公告)日：2002-05-07
申请号：US09729541
申请日：2000-12-04
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C1604
CPC分类号： G11C7/1093 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C11/4093 , G11C11/4096
摘要： A semiconductor memory device is provided in which no delay in writing of data occurs due to increases in the output load of the data input circuit, and which is also compatible with various bit configurations. The device comprises a plurality of data input circuits for inputting data from an external source, and a plurality of data write circuits for writing data input from the plurality of data input circuits to a memory cell array. The data to be stored is input from an external source by selectively using the plurality of data input circuits, and then each bit to be stored is distributed to the plurality of data write circuits according to the bit configuration of the data. Of the plurality of data input circuits, data input from a specific data input circuit is distributed to one of the plurality of data write circuits via another data input circuit.
摘要翻译：提供一种半导体存储器件，其中由于数据输入电路的输出负载的增加而不会导致数据写入延迟，并且其也与各种位配置兼容。该装置包括用于从外部源输入数据的多个数据输入电路和用于将从多个数据输入电路输入的数据写入存储单元阵列的多个数据写入电路。要存储的数据通过选择性地使用多个数据输入电路从外部源输入，然后根据数据的位配置将要存储的每个位分配给多个数据写入电路。在多个数据输入电路中，从特定数据输入电路输入的数据经由另一数据输入电路分配给多个数据写入电路中的一个。

35. 发明授权

US06353573B1 Clock synchronization semiconductor memory device 失效
标题翻译：时钟同步半导体存储器件
公开(公告)号：US06353573B1
公开(公告)日：2002-03-05
申请号：US09568348
申请日：2000-05-10
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C800
CPC分类号： G11C7/109 , G11C7/1072 , G11C7/1078 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4094
摘要： A clock synchronization semiconductor memory device in which the pre-charging time tRP can be accelerated by the variable delay time for write recovery. There is provided a unit for checking whether or not at least one clock cycle before the inputting of the pre-charge command is that for the write operation, and for holding the checked result. There is also provided a unit for performing switching control at the time of inputting the pre-charge command, responsive to the checked result, as to whether or not a pre-set delay time is to be introduced as from the time of inputting the pre-charge command until word line resetting.
摘要翻译：一种时钟同步半导体存储器件，其中可以通过用于写入恢复的可变延迟时间加速预充电时间tRP。提供了一个单元，用于检查在预充电命令的输入之前至少一个时钟周期是否是用于写入操作的单元，并且用于保持所检查的结果。还提供了一种用于在输入预充电命令时执行切换控制的单元，响应于检查结果，从输入预先设定的时间起是否要引入预设延迟时间充电命令直到字线复位。

36. 发明授权

US06272057B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06272057B1
公开(公告)日：2001-08-07
申请号：US09545884
申请日：2000-04-07
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C700
CPC分类号： G11C29/84
摘要： A semiconductor memory device is designed to speed up the selection of a word line. The semiconductor memory device comprises a plurality of normal row decoders for decoding input row address data for specifying word lines when access is made to those of memory cells of a memory cell array which are other than a redundant row of memory cells, thereby selecting those word lines to which those memory cells that are other than the redundant row of memory cells are connected; a redundant row decoder for specifying that word line to which the redundant row of memory cells is connected when access is made to any memory cell which belongs to the redundant row; decision means for determining whether or not to select a memory cell belonging to the redundant row based on the input row address data and selecting the redundant row decoder when selecting the memory cell belonging to the redundant row; and control means for changing only those word lines which are connected to the normal row decoders from an active state to a standby state based on a decision output of the decision means when the decision means has determined to select a memory cell belonging to the redundant row when changing the word lines connected to the normal row decoders from a standby state to an active state.
摘要翻译：半导体存储器件被设计成加速字线的选择。半导体存储器件包括多个正常行解码器，用于当对与存储器单元的冗余行不同的存储单元阵列的存储单元进行访问时，用于解码用于指定字线的输入行地址数据，从而选择这些字与存储器单元的冗余行不同的那些存储单元被连接到的行; 冗余行解码器，用于当对属于所述冗余行的任何存储单元进行访问时，指定所述冗余行存储单元连接到的字线; 决定装置，用于基于所输入的行地址数据确定是否选择属于所述冗余行的存储单元，并且在选择属于所述冗余行的存储单元时选择所述冗余行解码器; 以及控制装置，用于当判定装置确定选择属于冗余行的存储单元时，根据判定装置的判定输出，仅将那些连接到正常行解码器的字线从活动状态改变为待机状态当将连接到正常行解码器的字线从待机状态改变为活动状态时。

37. 发明授权

US6104224A Delay circuit device having a reduced current consumption 失效
标题翻译：具有降低的电流消耗的延迟电路装置
公开(公告)号：US6104224A
公开(公告)日：2000-08-15
申请号：US75531
申请日：1998-05-11
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G06F1/10 , G11C7/22 , G11C11/407 , G11C11/4076 , H03H11/26 , H03K5/13 , H03L7/00
CPC分类号： G11C7/22 , G11C11/4076 , H03K5/133 , H03K5/135
摘要： A delay circuit device having first and second delay circuits arrays so constructed that an output can be taken out from an arbitrary position of a signal transmission path, discriminating circuits receiving an output from two positions which divide the first delay circuit array into three portions, and three control circuits. The first and second delay circuit arrays are so arranged that the direction of signal transmission paths are opposite to each other. An output of the first delay circuit array is connected to an input of the second delay circuit array through the control circuits in the order from the position near to an input of the first delay circuit array and in the order from the position near to an output of the second delay circuit array. A first signal is supplied to the first delay circuit array, and whether or not the first signal is propagated to the output of the two positions is respectively latched in the discriminating circuits. When an arbitrary time has elapsed after the first signal is supplied, a second signal is supplied to not greater than four control circuits of the control circuits, in accordance with data latched in the discriminating circuits. The first signal on the first delay circuit array is transferred to the second delay circuit array, and the first signal on the first delay circuit array is removed. Thus, a clock having no phase difference from an external clock can be generated with a low current consumption, with a small number of periods, over a wide frequency range, and over a wide power supply voltage range.
摘要翻译：一种具有第一和第二延迟电路阵列的延迟电路装置，其结构使得输出可以从信号传输路径的任意位置取出，鉴别电路接收从第一延迟电路阵列分成三部分的两个位置的输出，以及三个控制电路。第一和第二延迟电路阵列被布置成使得信号传输路径的方向彼此相反。第一延迟电路阵列的输出通过控制电路以从接近第一延迟电路阵列的输入的位置起依次顺序连接到第二延迟电路阵列的输入，并且从接近输出的位置的第二延迟电路阵列。第一信号被提供给第一延迟电路阵列，并且第一信号是否传播到两个位置的输出分别被锁存在识别电路中。当在提供第一信号之后经过了任意时间时，根据锁存在识别电路中的数据，向不大于控制电路的四个控制电路提供第二信号。第一延迟电路阵列上的第一信号被传送到第二延迟电路阵列，并且第一延迟电路阵列上的第一信号被去除。因此，在宽的电源电压范围内，可以以较低的电流消耗，较小的周期，宽的频率范围内产生与外部时钟无相位差的时钟。

38. 发明授权

US5361000A Reference potential generating circuit 失效
标题翻译：参考电位发生电路
公开(公告)号：US5361000A
公开(公告)日：1994-11-01
申请号：US935209
申请日：1992-08-26
申请人： Yasuji Koshikawa , Tadahiko Sugibayashi
发明人： Yasuji Koshikawa , Tadahiko Sugibayashi
IPC分类号： G11C11/413 , G11C11/407 , H01L21/822 , H01L27/04 , H03K17/00 , H03K17/22 , H03K3/01
CPC分类号： H03K17/223 , H03K2217/0036
摘要： A reference potential generating circuit includes a plurality of MOS field effect transistors and a reference potential driver circuit. The MOS field effect transistors have different threshold voltages and a reference potential is obtained by amplifying the threshold voltage difference of the MOS field effect transistors. During the period in which a power supply potential externally supplied is lower than a predetermined target value of the reference potential, the reference potential driver circuit drives an output terminal for producing a potential corresponding to the power supply potential supplied externally. In this reference potential generating circuit, the S/N ratio is good and the circuit operation is stable, and is effective for reducing the power consumption and for increasing the integration density in semiconductor integrated circuit devices.
摘要翻译：参考电位产生电路包括多个MOS场效应晶体管和参考电位驱动电路。 MOS场效应晶体管具有不同的阈值电压，并且通过放大MOS场效应晶体管的阈值电压差来获得参考电位。在外部提供的电源电位低于基准电位的预定目标值的期间内，参考电位驱动电路驱动用于产生与外部提供的电源电位相对应的电位的输出端子。在该参考电位产生电路中，S / N比良好，电路运行稳定，对于降低功耗和提高半导体集成电路器件的集成密度是有效的。

39. 发明授权

US07613056B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07613056B2
公开(公告)日：2009-11-03
申请号：US12171081
申请日：2008-07-10
申请人： Sumio Ogawa , Yasuji Koshikawa
发明人： Sumio Ogawa , Yasuji Koshikawa
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired.The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block is logically allocated to the plurality of memory blocks in common.
摘要翻译：在设置有用于对缺陷存储单元进行修复的冗余电路的半导体存储器件中，可以有效地修复不均匀分布的存储单元缺陷。半导体存储器件具有多个存储块，并且存储块包括多个段。代替段的缺陷数据的冗余存储块物理地提供给多个存储块中的每一个。冗余存储器块的块地址被共同地逻辑地分配给多个存储器块。

40. 发明申请

US20090201753A1 Semiconductor memory device, control method therefor, and method for determining repair possibility of defective address 有权
标题翻译：半导体存储器件及其控制方法以及用于确定缺陷地址修复可能性的方法
公开(公告)号：US20090201753A1
公开(公告)日：2009-08-13
申请号：US12320892
申请日：2009-02-06
申请人： Yoshiro Riho , Jun Suzuki , Yasuhiro Matsumoto , Shuichi Kubouchi , Hiromasa Noda , Yasuji Koshikawa
发明人： Yoshiro Riho , Jun Suzuki , Yasuhiro Matsumoto , Shuichi Kubouchi , Hiromasa Noda , Yasuji Koshikawa
IPC分类号： G11C29/00 , G11C8/00 , G11C17/16
CPC分类号： G11C8/08 , G11C8/10 , G11C29/84
摘要： There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.
摘要翻译：提供有多个存储器垫，子字驱动器，其访问正常存储器单元，而不管请求访问的行地址是否是缺陷地址;子字驱动器，访问属于当行地址是缺陷地址时，由行地址指示的正常存储单元不同的存储器垫。根据本发明，正常存储单元和冗余存储单元属于彼此不同的存储器单元，从而可以在确定修复确定电路的操作的同时访问正常存储单元。

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