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31. 发明授权

US07859915B2 Semiconductor device and method of controlling the same 失效
标题翻译：半导体装置及其控制方法
公开(公告)号：US07859915B2
公开(公告)日：2010-12-28
申请号：US11770381
申请日：2007-06-28
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C7/10
CPC分类号： H01L27/115 , G11C29/20
摘要： A semiconductor device comprises a board, a first semiconductor storage device placed on the board, and a second semiconductor storage device placed on the board. Each of the first and second semiconductor storage devices has a first pad for inputting a chip enable signal, a second pad for inputting a write enable signal, a third pad for inputting an output enable signal, a fourth pad for inputting an address signal, and a fifth pad for inputting data. The first semiconductor storage device has a sixth pad which is electrically connected to the first pad of the second semiconductor device, and the second semiconductor storage device has a seventh pad which is electrically connected to the first pad of the first semiconductor device.
摘要翻译：一种半导体器件包括一个板，一个位于该板上的第一个半导体存储器件，以及一个位于该板上的第二个半导体存储器件。第一和第二半导体存储装置中的每一个具有用于输入芯片使能信号的第一焊盘，用于输入写使能信号的第二焊盘，用于输入输出使能信号的第三焊盘，用于输入地址信号的第四焊盘，以及用于输入数据的第五个垫。第一半导体存储装置具有电连接到第二半导体器件的第一焊盘的第六焊盘，并且第二半导体存储器件具有电连接到第一半导体器件的第一焊盘的第七焊盘。

32. 发明申请

US20090115500A1 VOLTAGE GENERATING CIRCUIT 失效
标题翻译：电压发生电路
公开(公告)号：US20090115500A1
公开(公告)日：2009-05-07
申请号：US12260366
申请日：2008-10-29
申请人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
发明人： Masaaki Kuwagata , Yasuhiko Honda , Yoshihiko Kamata
IPC分类号： G05F1/10
CPC分类号： G11C16/30 , G11C5/143 , G11C5/145 , H02M3/073 , H02M2001/0025 , H02M2001/0032 , Y02B70/16
摘要： A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit.
摘要翻译：用于从输出端子输出电压的电压产生电路具有连接在输出端子与地之间的第一分压电路; 连接在输出端和第一分压电路之间的开关电路; 第一电压检测电路，输出与比较结果对应的第一泵浦信号; 连接在输出端子和地之间的第二分压电路; 第二电压检测电路，其输出与比较结果相对应的第二泵浦信号; 输出从电源电压提升的电压的泵电路; 以及升压电路，其具有一端与第一分压电路的分压电阻连接的电容元件。

33. 发明授权

US07420863B2 Nonvolatile semiconductor memory device which stores multivalue data 失效
公开(公告)号：US07420863B2
公开(公告)日：2008-09-02
申请号：US11763743
申请日：2007-06-15
申请人： Yasuhiko Honda , Masao Kuriyama
发明人： Yasuhiko Honda , Masao Kuriyama
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634
摘要： A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

34. 发明授权

US07397716B2 Nonvolatile semiconductor memory device which stores multivalue data 有权
公开(公告)号：US07397716B2
公开(公告)日：2008-07-08
申请号：US11401286
申请日：2006-04-11
申请人： Yasuhiko Honda , Masao Kuriyama
发明人： Yasuhiko Honda , Masao Kuriyama
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634
摘要： A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

35. 发明授权

US07362587B2 Multi-chip package 失效
标题翻译：多芯片封装
公开(公告)号：US07362587B2
公开(公告)日：2008-04-22
申请号：US11677351
申请日：2007-02-21
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1066 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： A multi-chip package includes a first semiconductor memory controlled by a clock signal and an inverted clock signal, and a second semiconductor memory controlled by the clock signal. The first semiconductor memory and the second semiconductor memory each include a circuit for guaranteeing that a signal delay is suppressed between a peripheral circuit, and a pad to which the clock signal is input, a pad to which the inverted clock signal is input, a pad for outputting a data enable signal and a pad for outputting a data signal. Thus, it is guaranteed that the signal delay is suppressed, and the reliability of the multi-chip package is improved.
摘要翻译：多芯片封装包括由时钟信号和反相时钟信号控制的第一半导体存储器和由时钟信号控制的第二半导体存储器。第一半导体存储器和第二半导体存储器各自包括用于保证在外围电路和输入时钟信号的焊盘之间抑制信号延迟的电路，输入反相时钟信号的焊盘，焊盘用于输出数据使能信号和用于输出数据信号的焊盘。因此，可以保证信号延迟得到抑制，提高了多芯片封装的可靠性。

36. 发明授权

US07088631B2 Semiconductor storage apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US07088631B2
公开(公告)日：2006-08-08
申请号：US11019271
申请日：2004-12-23
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C7/02 , G11C7/12 , G11C16/24
摘要： A semiconductor storage apparatus includes a cell array including memory cells and reference cells, normal column selection transistors connected to columns of the memory cells, a normal data line array including normal data lines connected to columns of the memory cells, first dummy data lines formed of a same wiring layer of which the normal data lines are formed, a normal data line charging circuit, reference column selection transistors connected to reference columns of the reference cells, a reference data line array including reference data lines formed of a same wiring layer of which the normal data lines are formed, second dummy data lines formed of a same wiring layer of which the reference data lines are formed, a reference data line charging circuit, a first dummy data line charging circuit, a second dummy data line charging circuit, and a sense amplifier which senses data stored in the memory cells.
摘要翻译：一种半导体存储装置，包括：包括存储单元和参考单元的单元阵列，连接到存储单元的列的正常列选择晶体管，包括连接到存储单元的列的正常数据线的正常数据线阵列，由形成正常数据线的相同布线层，正常数据线充电电路，连接到参考单元的参考列的参考列选择晶体管，包括由相同布线层形成的参考数据线的参考数据线阵列形成正常的数据线，由形成基准数据线的相同布线层形成的第二虚拟数据线，参考数据线充电电路，第一虚拟数据线充电电路，第二虚拟数据线充电电路和感测放大器，其感测存储在存储单元中的数据。

37. 发明申请

US20050024942A1 SEMICONDUCTOR MEMORY DEVICE HAVING A BURST CONTINUOUS READ FUNCTION 有权
标题翻译：具有BURST连续读功能的半导体存储器件
公开(公告)号：US20050024942A1
公开(公告)日：2005-02-03
申请号：US10692329
申请日：2003-10-22
申请人： Yasuhiko Honda
发明人： Yasuhiko Honda
IPC分类号： G11C16/02 , G11C7/10 , G11C11/34 , G11C16/06 , G11C29/00
CPC分类号： G11C29/846 , G11C7/103 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： Several sense amplifiers detect data read from a memory cell of a bank in accordance with read address. Several first holding circuits individually hold data output from the sense amplifiers. Several second holding circuits hold data output from the corresponding first holding circuit after being delayed by time that the read address gains with respect to the burst address. Decoders individually supply data held in several second holding circuits to the corresponding line of a bus line.
摘要翻译：几个感测放大器根据读取地址检测从存储体的存储单元读取的数据。几个第一保持电路分别保存来自读出放大器的数据输出。几个第二保持电路在被读取地址相对于突发地址增益的时间延迟之后，保持来自对应的第一保持电路的数据输出。解码器将保持在几个第二保持电路中的数据单独提供给总线的相应线路。

38. 发明授权

US06829194B2 Semiconductor device that enables simultaneous read and write/read operation 有权
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US06829194B2
公开(公告)日：2004-12-07
申请号：US10307283
申请日：2002-12-02
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A memory cell array 1 has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided for writing data in memory cells in cores selected on the basis of a write command and for erasing data from selected blocks in cores selected on the basis of an erase command. Thus, there is realized a free core system capable of reading data out from memory cells in unselected cores while writing/erasing data in cores selected by the core selecting part.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义用作数据擦除单位的存储单元范围。半导体设备具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作在第一存储器和第二存储体，同时在第一和第二存储体的另一个中进行数据写入或擦除操作。

39. 发明授权

US06512693B2 Semiconductor device that enables simultaneous read and write/erase operation 有权
标题翻译：实现同时读/写/擦除操作的半导体器件
公开(公告)号：US06512693B2
公开(公告)日：2003-01-28
申请号：US09987981
申请日：2001-11-16
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C1604
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义作为数据擦除单位的存储单元的范围。半导体器件具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作以在第一和第二组中的另一个中进行数据写入或擦除操作的第一和第二存储体。

40. 发明申请

US20120155169A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120155169A1
公开(公告)日：2012-06-21
申请号：US13364496
申请日：2012-02-02
申请人： Yasuhiko Honda , Takahiro Suzuki , Masao Iwamoto , Kiyochika Kinjo
发明人： Yasuhiko Honda , Takahiro Suzuki , Masao Iwamoto , Kiyochika Kinjo
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C29/00
摘要： A nonvolatile semiconductor storage device storing plural data bits in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data. In a first write operation processing data in the first unit, logic of one of the higher-order and the lower-order bit is fixed, and two multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the memory cell in a pseudo binary state. In a second write operation processing data in a second unit larger than the first unit, plural input data bits in a multivalued state and parity data for error correction in the second unit are stored in the memory cell.
摘要翻译：一种非易失性半导体存储装置，其通过分配从第一单位中的一对数据中选择的高阶位和从所述一对数据中的另一个中选择的低位位选择多位数据来存储多个数据位在一个存储单元中。在第一单元中处理数据的第一写入操作中，高阶和低位中的一个的逻辑是固定的，并且分配两个阈值电压之间的差最大化的多值数据，从而存储一位输入存储单元中的伪二进制状态的数据。在第二写入操作中，处理大于第一单元的第二单元中的数据，多值状态中的多个输入数据位和第二单元中用于纠错的奇偶校验数据被存储在存储单元中。

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