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31. 发明授权

US06538273B2 Ferroelectric transistor and method for fabricating it 有权
标题翻译：铁电晶体管及其制造方法
公开(公告)号：US06538273B2
公开(公告)日：2003-03-25
申请号：US09849910
申请日：2001-05-04
申请人： Josef Willer , Georg Braun , Till Schlösser , Thomas Haneder
发明人： Josef Willer , Georg Braun , Till Schlösser , Thomas Haneder
IPC分类号： H01L2902
CPC分类号： H01L29/78391
摘要： A ferroelectric transistor is disclosed which has two source/drain regions and a channel region disposed in between in a semiconductor substrate. A metallic intermediate layer is disposed on the surface of the channel region and forms a Schottky diode with the semiconductor substrate, and a ferroelectric layer and a gate electrode are disposed on its surface. The ferroelectric transistor is fabricated using steps appertaining to silicon process technology.
摘要翻译：公开了具有两个源极/漏极区域和设置在半导体衬底之间的沟道区域的铁电晶体管。金属中间层设置在沟道区域的表面上，并与半导体衬底形成肖特基二极管，并且在其表面上设置铁电层和栅电极。铁电晶体管使用与硅工艺技术相关的步骤制造。

32. 发明授权

US06504200B2 DRAM cell configuration and fabrication method 有权
公开(公告)号：US06504200B2
公开(公告)日：2003-01-07
申请号：US09951243
申请日：2001-09-12
申请人： Till Schlösser , Bernhard Sell , Josef Willer
发明人： Till Schlösser , Bernhard Sell , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823
摘要： Bit lines are arranged in the lower parts of trenches of a substrate. Word lines are located above the substrate except for protuberances or bulges, which extend downwards into the trenches and which are arranged above the bit lines. The transistors are vertical transistors whose source/drain regions are located below the word lines and between adjacent trenches. The capacitors are linked with the upper source/drain regions. Conductive structures that surround the word lines from the top and the sides while being insulated from the word lines and bordering on the upper source/drain regions can link the upper source/drain regions with the capacitors.

33. 发明授权

US07595262B2 Manufacturing method for an integrated semiconductor structure 有权
标题翻译：集成半导体结构的制造方法
公开(公告)号：US07595262B2
公开(公告)日：2009-09-29
申请号：US11588591
申请日：2006-10-27
申请人： Till Schlösser
发明人： Till Schlösser
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/8236 , H01L21/8234 , H01L21/8242 , H01L21/336 , H01L21/44 , H01L21/28
CPC分类号： H01L27/10894 , H01L27/10882 , H01L27/10891
摘要： A manufacturing method for an integrated semiconductor structure and a corresponding semiconductor structure is disclosed. The method includes forming a peripheral circuitry in a peripheral device region, wherein the peripheral circuitry includes a peripheral transistor at least partially formed in the semiconductor substrate and having a first gate dielectric formed in a first high temperature process step. The method further includes forming a plurality of memory cells in a memory cell region, each of said memory cells including an access transistor at least partially formed in a semiconductor substrate and having a second gate dielectric formed in a second high temperature process step and having a metallic gate conductor. The first and second high temperature process steps are performed before a step of forming the metallic gate conductor.
摘要翻译：公开了一种用于集成半导体结构和相应的半导体结构的制造方法。该方法包括在外围设备区域中形成外围电路，其中外围电路包括至少部分地形成在半导体衬底中并具有在第一高温工艺步骤中形成的第一栅极电介质的外围晶体管。该方法还包括在存储器单元区域中形成多个存储单元，每个存储单元包括至少部分地形成在半导体衬底中并具有在第二高温工艺步骤中形成的第二栅电介质的存取晶体管，金属栅极导体。第一和第二高温工艺步骤在形成金属栅极导体的步骤之前进行。

34. 发明授权

US06939763B2 DRAM cell arrangement with vertical MOS transistors, and method for its fabrication 失效
标题翻译：具有垂直MOS晶体管的DRAM单元布置及其制造方法
公开(公告)号：US06939763B2
公开(公告)日：2005-09-06
申请号：US10720730
申请日：2003-11-24
申请人： Till Schlösser , Brian S. Lee
发明人： Till Schlösser , Brian S. Lee
IPC分类号： H01L21/02 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L27/12 , H01L29/786
CPC分类号： H01L27/10858 , H01L27/10852 , H01L27/10876
摘要： DRAM cell arrangement with vertical MOS transistors, and method for its fabrication. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors belonging to one row are parts of a strip-like word line, so that at each crossing point of the memory cell matrix there is a vertical dual-gate MOS transistor with gate electrodes of the associated word line formed in the trenches on both sides of the associated rib.
摘要翻译：具有垂直MOS晶体管的DRAM单元布置及其制造方法。沿着存储单元矩阵的一列排列的通道区域是由栅介质层包围的肋的部分。属于一行的MOS晶体管的栅电极是条状字线的一部分，因此在存储单元矩阵的每个交叉点存在垂直双栅极MOS晶体管，其中形成相关联的字线的栅电极相关肋骨两侧的沟槽。

35. 发明授权

US06838724B2 Transistor array and semiconductor memory configuration fabricated with the transistor array 有权
标题翻译：晶体管阵列和晶体管阵列制造的半导体存储器配置
公开(公告)号：US06838724B2
公开(公告)日：2005-01-04
申请号：US10718310
申请日：2003-11-20
申请人： Bernhard Kowalski , Andreas Felber , Valentin Rosskopf , Till Schlösser , Jürgen Lindolf
发明人： Bernhard Kowalski , Andreas Felber , Valentin Rosskopf , Till Schlösser , Jürgen Lindolf
IPC分类号： H01L21/8242 , H01L27/02 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10876 , H01L27/0207 , H01L27/10841 , H01L27/10891 , H01L29/945
摘要： A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of the transistors are located on both sides of active webs running parallel to one another and are connected to a superimposed metal plane by word line or CS contacts. To insulate these word line contacts from the other elements of the transistor array and of the cell array, the word line contacts are located in deep trenches that are introduced into the webs.
摘要翻译：晶体管阵列具有连接到存储单元阵列的存储电容器的垂直FET晶体管。晶体管的形成字线的栅电极条位于相互平行运行的有源网的两侧，并通过字线或CS触点连接到叠加的金属平面。为了将这些字线触点与晶体管阵列和单元阵列的其它元件绝缘，字线触点位于被引入幅材的深沟槽中。

36. 发明授权

US06798689B2 Integrated memory with a configuration of non-volatile memory cells and method for fabricating and for operating the integrated memory 有权
标题翻译：具有非易失性存储单元配置的集成存储器以及用于制造和运行集成存储器的方法
公开(公告)号：US06798689B2
公开(公告)日：2004-09-28
申请号：US10444546
申请日：2003-05-23
申请人： Gerhard Müller , Till Schlösser
发明人： Gerhard Müller , Till Schlösser
IPC分类号： G11C1100
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/15 , H01L27/228
摘要： An integrated memory with a configuration of non-volatile memory cells based on ferromagnetic storage contains both powerful memory cells with a magnetoresistive effect with a transistor control and cost-effective memory cells with a magnetoresistive effect with memory elements connected between the word lines and bit lines. The memory elements connected directly between the bit line and the word line are preferably inserted in memory cell arrays that can be stacked one above the other above the memory cells with the transistor, and thereby achieve a high integration density. The fact that the memory, which contains both types and thereby satisfies all the system requirements, is fabricated in one module and in one process sequence considerably lowers the fabrication costs.
摘要翻译：具有基于铁磁存储器的非易失性存储器单元的配置的集成存储器包含具有晶体管控制的磁阻效应的强大的存储单元和具有磁阻效应的具有成本效益的存储单元，存储元件连接在字线和位线之间。直接连接在位线和字线之间的存储元件优选地插入存储单元阵列中，该存储单元阵列可以用晶体管堆叠在存储单元之上，从而实现高积分密度。包含两种类型并因此满足所有系统要求的存储器被制造在一个模块中，并且在一个过程序列中大大降低了制造成本。

37. 发明授权

US06642565B2 Miniaturized capacitor with solid-state dielectric, in particular for integrated semiconductor memories, E.G. DRAMS, and method for fabricating such a capacitor 有权
公开(公告)号：US06642565B2
公开(公告)日：2003-11-04
申请号：US09935624
申请日：2001-08-23
申请人： Emmerich Bertagnolli , Till Schlösser , Josef Willer
发明人： Emmerich Bertagnolli , Till Schlösser , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L28/82
摘要： A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface made of tungsten silicide placed on a tungsten silicide layer which is disposed near a surface of a electrode body. The graining of the tungsten silicide layer is formed by tempering a temporarily present double layer that is formed of an understoichiometric tungsten silicide layer and a silicon layer. The double layer is formed on the tungsten silicide layer.

38. 发明授权

US06566187B1 DRAM cell system and method for producing same 有权
标题翻译： DRAM单元系统及其制造方法
公开(公告)号：US06566187B1
公开(公告)日：2003-05-20
申请号：US09806614
申请日：2001-05-11
申请人： Josef Willer , Franz Hoffmann , Till Schlösser
发明人： Josef Willer , Franz Hoffmann , Till Schlösser
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10841
摘要： DRAM cell arrangement and method for fabricating it Word lines and bit lines are arranged above a main area of a substrate, with the result that they have a planar construction and can be produced together with gate electrodes of transistors of a periphery of the cell arrangement. A depression of the substrate is provided per memory cell, a storage node of a storage capacitor being arranged in the lower region of said depression and a gate electrode of a vertical transistor being arranged in the upper region of said depression. The depressions of the memory cells are arranged between trenches filled with isolating structures. Upper source/drain regions of the transistors are arranged between two mutually adjacent isolating structures and between two mutually adjacent depressions. Lower source/drain regions are arranged in the substrate and adjoin the storage nodes. For process steps, alignment tolerances are so large that the space requirement for the memory cell can amount to 4F2.
摘要翻译： DRAM单元布置及其制造方法字线和位线布置在基板的主区域上方，结果是它们具有平面结构，并且可以与单元布置的外围的晶体管的栅电极一起生成。每个存储单元提供基板的凹陷，存储电容器的存储节点布置在所述凹陷的下部区域中，并且垂直晶体管的栅电极布置在所述凹陷的上部区域中。存储单元的凹陷布置在填充有隔离结构的沟槽之间。晶体管的上部源极/漏极区域布置在两个相互相邻的隔离结构之间以及两个彼此相邻的凹陷之间。下部源极/漏极区域布置在衬底中并与存储节点相邻。对于工艺步骤，对准公差如此大，使得存储器单元的空间需求可以达到4F2。

39. 发明授权

US06462979B2 Integrated memory having memory cells with magnetoresistive storage effect 有权
标题翻译：具有具有磁阻存储效应的存储单元的集成存储器
公开(公告)号：US06462979B2
公开(公告)日：2002-10-08
申请号：US09799626
申请日：2001-03-05
申请人： Till Schlösser , Roland Thewes
发明人： Till Schlösser , Roland Thewes
IPC分类号： G11C1100
CPC分类号： G11C11/15 , G11C11/16
摘要： The integrated memory has memory cells with a magnetoresistive storage effect in a memory cell array in the form of a matrix. The memory cells are each connected between one of the column lines and one of the row lines. The column lines are each connected to a read amplifier for reading a data signal from a memory cell. The read amplifier has an operational amplifier with feedback, and a first control input connected to one of the column lines. A capacitor is connected between a second control input of the operational amplifier and a terminal for a supply potential and is used to compensate for any offset voltage at the control inputs of the operational amplifier. This allows a data signal which is to be read from one of the memory cells to be detected comparatively reliably.
摘要翻译：集成存储器具有在矩阵形式的存储单元阵列中具有磁阻存储效应的存储单元。存储单元各自连接在一列列线和一行行之间。列线各自连接到用于从存储器单元读取数据信号的读取放大器。读取放大器具有带有反馈的运算放大器，以及连接到列线之一的第一控制输入。电容器连接在运算放大器的第二控制输入端和电源端之间，用于补偿运算放大器的控制输入端的任何偏移电压。这允许相对可靠地检测从一个存储单元读取的数据信号。

40. 发明授权

US06258656B1 Capacitor with high-&egr; dielectric or ferroelectric material based on the fin stack principle and production process using a negative mold 有权
标题翻译：电容器采用高电介质或铁电材料，基于散热片堆叠原理和生产工艺使用负模
公开(公告)号：US06258656B1
公开(公告)日：2001-07-10
申请号：US09395316
申请日：1999-09-13
申请人： Gerrit Lange , Till Schlösser
发明人： Gerrit Lange , Till Schlösser
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/88
摘要： A capacitor on a semiconductor configuration is formed with a high-&egr; dielectric or a ferroelectric material. A first noble-metal-containing storage electrode has a plurality of horizontal lamellae connected to one another via a support structure. The support structure is arranged on one or preferably two opposite external flanks of the lamellae. During production, firstly (inter alia by deposition of a sequence of layers with an alternating low and high etching rate) a fin stack negative mold, in particular made from p+-polysilicon, is formed, which is then filled conformally with the electrode material.
摘要翻译：半导体结构的电容器由高电介质或铁电材料形成。第一含贵金属的储存电极具有经由支撑结构彼此连接的多个水平薄片。支撑结构布置在薄片的一个或优选两个相对的外侧面上。在生产过程中，首先（尤其是通过沉积具有交替的低和高蚀刻速率的一系列层），形成特别由p +多晶硅制成的翅片堆叠阴模，然后将其与电极材料共形地填充。

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