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31. 发明授权

US08090984B2 Error detection and communication of an error location in multi-processor data processing system having processors operating in Lockstep 有权
标题翻译：在具有在Lockstep中操作的处理器的多处理器数据处理系统中错误检测和通信错误位置
公开(公告)号：US08090984B2
公开(公告)日：2012-01-03
申请号：US12331759
申请日：2008-12-10
申请人： William C. Moyer , Michael J. Rochford , Davide M. Santo
发明人： William C. Moyer , Michael J. Rochford , Davide M. Santo
IPC分类号： G06F11/00 , G06F11/16
CPC分类号： G06F11/1641 , G06F11/1658 , G06F11/1687
摘要： A system and method are provided. The system comprises a first and second processor, and a cross-signaling interface. The first processor executes instructions. The second processor executes the instructions in lockstep with the first processor. The cross-signaling interface is coupled between the first and second processors and is for signaling both an unanticipated altered state a location of the unanticipated altered state in the first processor to the second processor to cause the second processor to emulate the unanticipated altered state in lockstep with the first processor. The method comprises: executing instructions in a first processor; executing the instructions in a second processor in lockstep with the first processor; detecting an error condition in the first processor; transmitting information about the error condition to the second processor; processing the error condition in the first processor; and causing the first and second processor to emulate the error condition in lockstep.
摘要翻译：提供了一种系统和方法。该系统包括第一和第二处理器以及交叉信令接口。第一个处理器执行指令。第二处理器与第一处理器在锁定状态下执行指令。交叉信令接口耦合在第一处理器和第二处理器之间，用于将未预期的改变状态的信号发送到第一处理器中的意料之外的改变状态的位置到第二处理器，以使第二处理器在锁步骤中模拟意外的改变状态与第一个处理器。该方法包括：在第一处理器中执行指令; 在与第一处理器锁定的步骤中在第二处理器中执行指令; 检测所述第一处理器中的错误状况; 将关于所述错误状况的信息发送到所述第二处理器; 处理第一处理器中的错误状况; 并使第一和第二处理器在锁步骤中模拟错误状况。

32. 发明授权

US08001591B2 Distributed resource access protection 有权
标题翻译：分布式资源访问保护
公开(公告)号：US08001591B2
公开(公告)日：2011-08-16
申请号：US11343454
申请日：2006-01-31
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F7/00
CPC分类号： G06F12/1483
摘要： A method includes determining, at a first requesting component of an integrated circuit device, a first key value based on a first set of one or more bits of a first address associated with a first access request of the first requesting component. The method further includes transmitting the first key value from the first requesting component to a resource component of the integrated circuit device. The method also includes determining, at the resource component, an authorization of the first access request based on the first key value and a second set of one or more bits of the first address.
摘要翻译：一种方法包括：在集成电路设备的第一请求组件处，基于与第一请求组件的第一访问请求相关联的第一地址的一个或多个位的第一集合来确定第一密钥值。该方法还包括将第一密钥值从第一请求组件传输到集成电路设备的资源组件。所述方法还包括在所述资源组件的基础上，基于所述第一密钥值和所述第一地址的一个或多个比特的第二组确定所述第一访问请求的授权。

33. 发明申请

US20110191602A1 PROCESSOR WITH SELECTABLE LONGEVITY 审中-公开
标题翻译：具有可选择长度的处理器
公开(公告)号：US20110191602A1
公开(公告)日：2011-08-04
申请号：US12696633
申请日：2010-01-29
申请人： David R. Bearden , Ravindraraj Ramaraju , Peter P. Abramowitz , William C. Moyer
发明人： David R. Bearden , Ravindraraj Ramaraju , Peter P. Abramowitz , William C. Moyer
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A processor and method has at least one processor core for processing information and receives an operating voltage for powering circuitry of the processor. A selector receives a value indicative of a temperature within the processor and receives a value from a plurality of possible longevity values that each indicates a predetermined desired longevity of valid operation of the processor. An output provides an identifier that controls at least one of an operating voltage or an operating frequency of the processor, wherein the identifier provided is at least based on the value indicative of temperature and the predetermined desired longevity. A reliability storage device coupled to the selector stores the value from the plurality of possible longevity values that each indicates the predetermined desired longevity of valid operation of the processor.
摘要翻译：处理器和方法具有用于处理信息的至少一个处理器核心并且接收用于为处理器的电路供电的工作电压。选择器接收指示处理器内的温度的值，并从多个可能的寿命值接收值，每个可能的寿命值指示处理器的有效操作的预定期望寿命。输出提供控制处理器的操作电压或操作频率中的至少一个的标识符，其中提供的标识符至少基于指示温度和预定期望寿命的值。耦合到选择器的可靠性存储设备存储来自多个可能的寿命值的值，每个可能的寿命值指示处理器的有效操作的预定期望寿命。

34. 发明授权

US07984337B2 Address translation trace message generation for debug 有权
标题翻译：地址转换跟踪消息生成调试
公开(公告)号：US07984337B2
公开(公告)日：2011-07-19
申请号：US12389153
申请日：2009-02-19
申请人： William C. Moyer , Richard G. Collins
发明人： William C. Moyer , Richard G. Collins
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3648 , G06F12/10
摘要： A data processing system and method generates debug messages by permitting an external debug tool to have real-time trace functionality. A data processor executes a plurality of data processing instructions and uses a memory for information storage. Debug circuitry generates debug messages including address translation trace messages. A memory management unit has address translation logic for implementing address translation to translate addresses between virtual and physical forms. The debug circuitry includes message generation circuitry that is coupled to the memory management unit for receiving notice when one or more address translation mappings are modified. The message generation circuitry generates an address translation trace message in response to a detection of a modification of an address translation mapping occurs and provides the address translation trace message external to the debug circuitry.
摘要翻译：数据处理系统和方法通过允许外部调试工具具有实时追踪功能来生成调试消息。数据处理器执行多个数据处理指令并使用存储器进行信息存储。调试电路生成调试消息，包括地址转换跟踪消息。存储器管理单元具有用于实现地址转换以在虚拟和物理形式之间转换地址的地址转换逻辑。调试电路包括消息产生电路，其耦合到存储器管理单元，用于在修改一个或多个地址转换映射时接收通知。消息生成电路响应于对地址转换映射的修改的检测而产生地址转换跟踪消息，并且将调试电路外部的地址转换跟踪消息提供给该消息生成电路。

35. 发明授权

US07958401B2 Debug trace messaging with one or more characteristic indicators 有权
标题翻译：使用一个或多个特征指示器调试跟踪消息
公开(公告)号：US07958401B2
公开(公告)日：2011-06-07
申请号：US12179631
申请日：2008-07-25
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F11/00
CPC分类号： G06F11/3648
摘要： In a data processing system, an address associated with a processing operation is received. A modified address is generated which includes a characteristic indicator within the address at a first predetermined bit position when the characteristic indicator is of a first type or at a second predetermined bit position when the characteristic indicator is of a second type. A first value of the characteristic indicator indicates a characteristic of the address. A modified address may also be generated which includes a characteristic indicator at a first predetermined bit position when a position indicator has a first value or at a second predetermined bit position when the position indicator has a second value. Address information can then be generated from the modified address, and a debug message can be created which includes the address information.
摘要翻译：在数据处理系统中，接收与处理操作相关联的地址。当特征指示符是第二类型时，当特征指示符是第一类型时或在第二预定比特位置时，产生修改后的地址，该地址包括在第一预定比特位置的地址内的特征指示符。特征指示符的第一个值表示地址的特征。当位置指示器具有第一值时或者当位置指示器具有第二值时，还可以产生包括第一预定位位置处的特性指示符的修改的地址。然后可以从修改的地址生成地址信息，并且可以创建包括地址信息的调试消息。

36. 发明授权

US07958173B2 Population count approximation circuit and method thereof 有权
标题翻译：人口数近似电路及其方法
公开(公告)号：US07958173B2
公开(公告)日：2011-06-07
申请号：US11777664
申请日：2007-07-13
申请人： William C. Moyer , Kelly K. Taylor
发明人： William C. Moyer , Kelly K. Taylor
IPC分类号： G06F7/00
CPC分类号： G06F7/607
摘要： A circuit and method provides an estimate of a population count (popcount) of a plurality of input bit values. In one form the input bit values represent respective nodes of an integrated circuit. An approximation circuit uses an approximation input stage which receives a plurality of data inputs and has a plurality of logic circuits. Each logic circuit provides a single bit output. The approximation circuit provides monotonic accuracy. A reduction tree receives the single bit outputs of the plurality of logic circuits and provides an approximate count of how many of the plurality of data inputs are asserted. Size and speed are improved by providing the estimate as opposed to an exact value.
摘要翻译：电路和方法提供对多个输入比特值的总体数（估计）的估计。在一种形式中，输入位值表示集成电路的各个节点。近似电路使用接收多个数据输入并具有多个逻辑电路的近似输入级。每个逻辑电路提供单个位输出。近似电路提供单调精度。还原树接收多个逻辑电路的单个位输出，并且提供多个数据输入中有多少被断言的近似计数。通过提供估计而不是精确值来改善尺寸和速度。

37. 发明授权

US07937573B2 Metric for selective branch target buffer (BTB) allocation 有权
标题翻译：用于选择性分支目标缓冲区（BTB）分配的度量标准
公开(公告)号：US07937573B2
公开(公告)日：2011-05-03
申请号：US12040210
申请日：2008-02-29
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/32 , G06F9/34
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3804 , G06F9/382
摘要： A method and data processing system allocates entries in a branch target buffer (BTB). Instructions are fetched from a plurality of instructions and one of the plurality of instructions is determined to be a branch instruction. A corresponding branch target address is determined. A determination is made whether the branch target address is stored in a branch target buffer (BTB). When the branch target address is not stored in the branch target buffer, an entry in the branch target buffer is identified for allocation to receive the branch target address based upon stored metrics such as data processing cycle saving information and branch prediction state. In one form the stored metrics are stored in predetermined fields of the entries of the BTB.
摘要翻译：方法和数据处理系统在分支目标缓冲器（BTB）中分配条目。指令从多个指令中取出，并且多个指令中的一个被确定为分支指令。确定相应的分支目标地址。确定分支目标地址是否存储在分支目标缓冲器（BTB）中。当分支目标地址未被存储在分支目标缓冲器中时，识别分支目标缓冲器中的条目用于分配以基于存储的诸如数据处理周期保存信息和分支预测状态的指标来接收分支目标地址。在一种形式中，存储的度量被存储在BTB的条目的预定字段中。

38. 发明授权

US07931190B2 Circuit and method for correlated inputs to a population count circuit 有权
标题翻译：电路和方法，用于与人口计数电路相关的输入
公开(公告)号：US07931190B2
公开(公告)日：2011-04-26
申请号：US11777650
申请日：2007-07-13
申请人： William C. Moyer , Kelly K. Taylor
发明人： William C. Moyer , Kelly K. Taylor
IPC分类号： G06C29/00
CPC分类号： G06F7/607
摘要： A circuit includes a plurality of selection circuits. Each of the plurality of selection circuits has a first input, a second input, a control input, and an output. Each of the first inputs receives one of a plurality of correlated signals. Each of the second inputs receives one of a plurality of uncorrelated signals. Each of the control inputs receives a correlation mode control signal, and each of the outputs provides the one of the plurality of correlated signals or the one of the plurality of uncorrelated signals based on the correlation mode control signal. The circuit further includes a population count circuit having a plurality of data inputs coupled to receive the outputs of the plurality of selection circuits. The population count circuit provides a population count for the plurality of data inputs. The population count may be an approximate count or an accurate count.
摘要翻译：电路包括多个选择电路。多个选择电路中的每一个具有第一输入，第二输入，控制输入和输出。每个第一输入端接收多个相关信号中的一个。每个第二输入接收多个不相关信号中的一个。每个控制输入接收相关模式控制信号，并且每个输出基于相关模式控制信号提供多个相关信号中的一个或多个不相关信号中的一个。电路还包括具有耦合以接收多个选择电路的输出的多个数据输入的总体计数电路。人口计数电路为多个数据输入提供总体计数。人口数量可能是近似计数或准确计数。

39. 发明授权

US07895422B2 Selective postponement of branch target buffer (BTB) allocation 有权
标题翻译：分支目标缓冲区（BTB）分配的选择性推迟
公开(公告)号：US07895422B2
公开(公告)日：2011-02-22
申请号：US12040204
申请日：2008-02-29
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/38 , G06F9/44
CPC分类号： G06F9/3806 , G06F9/3802 , G06F9/3814 , G06F9/3844
摘要： A system and method provides branch target buffer (BTB) allocation. When a branch instruction is received, a branch target address that corresponds to the branch instruction is determined. A determination is made whether the branch target address is presently stored in a branch target buffer (BTB). When the branch target address is not presently stored in the branch target buffer, an entry in the branch target buffer is identified to receive the branch target address. A value in a field within the identified entry in the branch target buffer, such as a postponement flag (PF), is used to selectively override a replacement decision defined by predetermined branch target buffer allocation criteria. In one form, if a branch is taken, the identified entry is replaced with the branch target address in response to determining that the value in the field within the identified entry has a predetermined value.
摘要翻译：系统和方法提供分支目标缓冲区（BTB）分配。当接收到分支指令时，确定与分支指令对应的分支目标地址。确定分支目标地址是否当前存储在分支目标缓冲器（BTB）中。当分支目标地址当前不存储在分支目标缓冲器中时，识别分支目标缓冲器中的条目以接收分支目标地址。使用分支目标缓冲器中的所识别的条目中的字段中的值（诸如推迟标志（PF））来选择性地覆盖由预定分支目标缓冲器分配标准定义的替换决策。在一种形式中，如果采取分支，则响应于确定所识别的条目中的字段中的值具有预定值，将所标识的条目替换为分支目标地址。

40. 发明授权

US07870430B2 Method and apparatus for sharing debug resources 有权
标题翻译：共享调试资源的方法和装置
公开(公告)号：US07870430B2
公开(公告)日：2011-01-11
申请号：US12040215
申请日：2008-02-29
申请人： Alistair P. Robertson , William C. Moyer , Ray C. Marshall
发明人： Alistair P. Robertson , William C. Moyer , Ray C. Marshall
IPC分类号： G06F11/00
CPC分类号： G06F11/3648 , G06F11/2236
摘要： A method includes providing an integrated circuit having a plurality of debug resources. The debug resources are usable exclusively for debug operations. The debug operations include operations directed by debug software executed by the integrated circuit and operations directed by external debug hardware which is external to the integrated circuit. The method further includes enabling availability of a first portion of the debug resources for use by the debug software, where a second portion of the debug resources are committed for exclusive use by the external debug hardware. The first portion is exclusive of the second portion. The method includes performing operations directed by the debug software using at least one debug resource of the first portion of the debug resources and operations directed by the external debug hardware using at least one debug resource of the second portion of the debug resources.
摘要翻译：一种方法包括提供具有多个调试资源的集成电路。调试资源专用于调试操作。调试操作包括由集成电路执行的调试软件和由集成电路外部的外部调试硬件引导的操作所执行的操作。该方法还包括使得调试资源的第一部分的可用性被调试软件使用，其中调试资源的第二部分被提交供外部调试硬件专用。第一部分不包括第二部分。该方法包括使用调试资源的第一部分的至少一个调试资源和外部调试硬件使用调试资源的第二部分的至少一个调试资源来执行的操作来执行由调试软件执行的操作。

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