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31. 发明授权

US6125050A Configuration for driving parallel lines in a memory cell configuration 有权
标题翻译：用于驱动存储单元配置中的并行线的配置
公开(公告)号：US6125050A
公开(公告)日：2000-09-26
申请号：US335365
申请日：1999-06-17
申请人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul-Werner Basse , Wolfgang Krautschneider
发明人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul-Werner Basse , Wolfgang Krautschneider
IPC分类号： H01L27/112 , G11C5/02 , H01L21/8246
CPC分类号： H01L27/0207 , H01L27/1126 , H01L27/11293 , H01L27/11803
摘要： Parallel lines, for example bit lines in a memory cell configuration formed of doped regions in a semiconductor substrate, are driven by electrically connecting a number of the lines to one another and to a common node. A number of selection lines extend transversely to the lines. MOS transistors are arranged at the points of intersection and are connected in series along one of the lines. The gate electrode of the MOS transistors is formed by the corresponding selection line. At least one MOS transistor in each of the parallel lines has a higher threshold voltage than the others.
摘要翻译：平行线，例如由半导体衬底中的掺杂区形成的存储单元配置中的位线，通过将多个线彼此电连接并连接到公共节点来驱动。多条选择线横向延伸。 MOS晶体管布置在交点处，并沿着一条线串联连接。 MOS晶体管的栅电极由相应的选择线形成。每条并行线路中的至少一个MOS晶体管的阈值电压高于其他。

32. 发明申请

US20050104117A1 Charge-trapping memory device and methods for operating and manufacturing the cell 有权
标题翻译：电荷捕获存储器件以及用于操作和制造电池的方法
公开(公告)号：US20050104117A1
公开(公告)日：2005-05-19
申请号：US10715142
申请日：2003-11-17
申请人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
发明人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
IPC分类号： G11C16/04 , H01L21/28 , H01L21/8246 , H01L27/115 , H01L29/792 , H01L29/788
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is performed by injection of hot holes into the strips individually for two-bit storage.
摘要翻译：电荷捕获层包括在源极和漏极结上方的两个条带。选择电荷俘获层和栅极电介质的厚度，以便在擦除过程中促进Fowler-Nordheim隧穿隧道的电子。通过将热孔单独注入热孔进行两位存储来执行编程。

33. 发明授权

US06614066B2 Ferroelectric transistor and memory cell configuration with the ferroelectric transistor 失效
公开(公告)号：US06614066B2
公开(公告)日：2003-09-02
申请号：US10113418
申请日：2002-04-01
申请人： Reinhard Stengl , Hans Reisinger , Thomas Haneder , Harald Bachhofer
发明人： Reinhard Stengl , Hans Reisinger , Thomas Haneder , Harald Bachhofer
IPC分类号： H01L2976
CPC分类号： H01L29/516 , H01L29/78391
摘要： A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

34. 发明授权

US06365944B1 Memory cell configuration and method for fabricating it 有权
标题翻译：存储单元配置及其制造方法
公开(公告)号：US06365944B1
公开(公告)日：2002-04-02
申请号：US09668485
申请日：2000-09-25
申请人： Hans Reisinger
发明人： Hans Reisinger
IPC分类号： H01L31113
CPC分类号： H01L27/11568 , H01L27/115
摘要： The invention relates to a memory cell configuration in which a plurality of memory cells are present in the region of a main area of a semiconductor substrate (10), and in which the memory cells each contain at least one MOS transistor having a source (29), gate (WL1 and WL2) and drain (60). The memory cells are configured in memory cell rows which run essentially parallel, in which adjacent memory cell rows are insulated by an isolation trench (20), in which adjacent memory cell rows each contain at least one bit line (60), and where the bit lines (60) of two adjacent memory cell rows face one another. The memory cell configuration is constructed in such a way that the isolation trench (20) penetrates more deeply into the semiconductor substrate (10) than the bit lines (60), and at least one of the source (29) and/or of the drain is at least partially situated underneath the isolation trench (20). The invention furthermore relates to a method for fabricating this memory cell configuration.
摘要翻译：本发明涉及一种存储单元结构，其中多个存储单元存在于半导体衬底（10）的主区域的区域中，并且其中存储单元各自包含至少一个具有源极（29）的MOS晶体管），栅极（WL1和WL2）和漏极（60）。存储器单元被配置在基本上平行的存储单元行中，其中相邻的存储单元行被隔离沟槽（20）绝缘，其中相邻存储单元行各自包含至少一个位线（60），并且其中两个相邻的存储单元行的位线（60）彼此面对。存储单元配置被构造成使得隔离沟槽（20）比位线（60）更深地穿入半导体衬底（10），并且源极（29）和/或漏极至少部分地位于隔离沟槽（20）下方。本发明还涉及一种用于制造该存储单元配置的方法。

35. 发明授权

US06191459B1 Electrically programmable memory cell array, using charge carrier traps and insulation trenches 失效
标题翻译：电可编程存储单元阵列，使用电荷载流子阱和绝缘沟槽
公开(公告)号：US06191459B1
公开(公告)日：2001-02-20
申请号：US08780488
申请日：1997-01-08
申请人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer , Hans Reisinger
发明人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer , Hans Reisinger
IPC分类号： H01L2976
CPC分类号： H01L29/7926 , H01L27/115 , H01L27/11556 , H01L29/792
摘要： An electrically programmable memory cell array is formed of memory cells, which include a vertical MOS transistor. The MOS transistor has a gate dielectric of a material with charge carrier traps. The memory cells are disposed along opposite edges of striplike, parallel insulation trenches. The width and spacing of the insulation trenches are preferably identical. The space required per memory cell of the memory cell array is 2F2, where F is the minimum structural size in the technology employed. The memory cells are programmed by selectively injecting electrons into the gate dielectric.
摘要翻译：电可编程存储单元阵列由包括垂直MOS晶体管的存储单元形成。 MOS晶体管具有具有电荷载流子阱的材料的栅极电介质。存储单元沿带状平行绝缘沟槽的相对边缘设置。绝缘沟槽的宽度和间距优选相同。存储单元阵列每个存储单元所需的空间为2F2，其中F为所采用技术中的最小结构尺寸。通过选择性地将电子注入到栅极电介质中来对存储器单元进行编程。

36. 发明授权

US6153475A Method for the manufacturing a memory cell configuration 失效
标题翻译：制造存储单元配置的方法
公开(公告)号：US6153475A
公开(公告)日：2000-11-28
申请号：US331495
申请日：1999-06-21
申请人： Franz Hofmann , Josef Willer , Hans Reisinger , Wolfgang Krautschneider , Paul-Werner von Basse
发明人： Franz Hofmann , Josef Willer , Hans Reisinger , Wolfgang Krautschneider , Paul-Werner von Basse
IPC分类号： H01L21/8246 , H01L27/112 , H01L21/336
CPC分类号： H01L27/112
摘要： For the manufacture of a memory cell arrangement with first memory cells that comprise a vertical MOS transistor and with second memory cells that do not comprise an MOS transistor, whereby the memory cells are arranged along opposite edges of strip-type trenches, memory cells that are adjacent along the trenches (5) are manufactured successively. The spacing of adjacent memory cells is determined in particular by means of a spacer technology. By this means, a space requirement per memory cell of 1F.sup.2 can be realized, whereby F is the minimum structural size of the respective technology.
摘要翻译： PCT No.PCT / DE97 / 02549 Sec。 371 1999年6月21日第 102（e）日期1999年6月21日PCT 1997年11月4日PCT PCT。第WO98 / 27586号公报日期1998年6月25日为了制造具有包括垂直MOS晶体管的第一存储单元和不包括MOS晶体管的第二存储单元的存储单元布置，由此存储单元沿带状沟槽的相对边缘布置沿着沟槽（5）相邻的存储单元依次制造。特别是通过间隔物技术来确定相邻存储单元的间隔。通过这种方式，可以实现1F2的每个存储单元的空间要求，由此F是相应技术的最小结构尺寸。

37. 发明授权

US6118159A Electrically programmable memory cell configuration 失效
标题翻译：电可编程存储单元配置
公开(公告)号：US6118159A
公开(公告)日：2000-09-12
申请号：US259376
申请日：1999-02-26
申请人： Josef Willer , Franz Hofmann , Hans Reisinger , Emmerich Bertagnolli , Bernd Gobel , Barbara Hasler , Karl-Heinz Tietgen
发明人： Josef Willer , Franz Hofmann , Hans Reisinger , Emmerich Bertagnolli , Bernd Gobel , Barbara Hasler , Karl-Heinz Tietgen
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/76 , H01L29/788
CPC分类号： H01L27/11517 , H01L27/115
摘要： The memory cell configuration comprises vertical transistors which are connected in a NOR architecture. The vertical transistors are disposed on flanks of trenches. Each vertical transistor includes an electrically insulated floating gate electrode, whose charge can be varied by Fowler-Nordheim tunneling due to a voltage drop between a control gate electrode and a source/drain region. The length of a coupling area in a direction parallel to a channel width, between the control gate electrode and the floating gate electrode is less than the channel width, in order to reduce the operating voltage. This is achieved by thermal oxidation of parts of the flanks of the trenches. Transistors which are adjacent in a direction transverse to the trenches share bit lines. Each bit line has a lightly doped first part and a highly doped second part. The coupling area can be enlarged even further by using a strip-shaped mask, which is extended by spacers.
摘要翻译：存储单元配置包括以NOR架构连接的垂直晶体管。垂直晶体管设置在沟槽的侧面。每个垂直晶体管包括电绝缘浮栅，其电荷可以由于控制栅极电极和源极/漏极区域之间的压降而由Fowler-Nordheim隧穿而改变。为了降低工作电压，与控制栅电极和浮置栅电极之间的通道宽度平行的方向上的耦合区域的长度小于沟道宽度。这是通过沟槽侧面部分的热氧化实现的。在横向于沟槽的方向上相邻的晶体管共享位线。每个位线具有轻掺杂的第一部分和高度掺杂的第二部分。通过使用由间隔物延伸的带状掩模，可以进一步扩大耦合面积。

38. 发明授权

US5994746A Memory cell configuration and method for its fabrication 有权
标题翻译：存储单元配置及其制造方法
公开(公告)号：US5994746A
公开(公告)日：1999-11-30
申请号：US232083
申请日：1999-01-15
申请人： Hans Reisinger , Reinhard Stengl , Franz Hofmann , Wolfgang Krautschneider , Josef Willer
发明人： Hans Reisinger , Reinhard Stengl , Franz Hofmann , Wolfgang Krautschneider , Josef Willer
IPC分类号： G11C17/08 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115
CPC分类号： H01L27/11273 , H01L27/112
摘要： The memory cell has transistors that are arranged three-dimensionally. Vertical MOS transistors are arranged on the sidewalls of semiconductor webs, and a plurality of transistors are arranged one above the other on each sidewall. The transistors that are arranged one above the other on a sidewall are connected in series.
摘要翻译：存储单元具有三维布置的晶体管。垂直MOS晶体管布置在半导体薄片的侧壁上，并且多个晶体管彼此并排设置在每个侧壁上。在侧壁上一个上下配置的晶体管串联连接。

39. 发明授权

US07049651B2 Charge-trapping memory device including high permittivity strips 有权
标题翻译：电荷捕获存储器件包括高电容率带
公开(公告)号：US07049651B2
公开(公告)日：2006-05-23
申请号：US10715142
申请日：2003-11-17
申请人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
发明人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is performed by injection of hot holes into the strips individually for two-bit storage.
摘要翻译：电荷捕获层包括在源极和漏极结上方的两个条带。选择电荷俘获层和栅极电介质的厚度，以便在擦除过程中促进Fowler-Nordheim隧穿隧道的电子。通过将热孔单独注入热孔进行两位存储来执行编程。

40. 发明授权

US06710388B2 Ferroelectric transistor, use thereof in a memory cell configuration and method of producing the ferroelectric transistor 有权
标题翻译：铁电晶体管，其在存储单元结构中的应用和制造铁电晶体管的方法
公开(公告)号：US06710388B2
公开(公告)日：2004-03-23
申请号：US09801209
申请日：2001-03-07
申请人： Thomas Peter Haneder , Hans Reisinger , Reinhard Stengl , Harald Bachhofer , Hermann Wendt , Wolfgang Hönlein
发明人： Thomas Peter Haneder , Hans Reisinger , Reinhard Stengl , Harald Bachhofer , Hermann Wendt , Wolfgang Hönlein
IPC分类号： H01L27108
CPC分类号： G11C11/22 , H01L29/78391
摘要： A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.
摘要翻译：适合作为存储元件的铁电晶体管具有设置在半导体衬底的表面上并设置在源极/漏极区之间的第一栅极中间层和第一栅电极。第一栅极中间层包含至少一个铁电层。除了第一栅极中间层之外，在源极/漏极区域之间配置第二栅极中间层和第二栅极电极。第二栅极中间层包含电介质层。第一栅电极和第二栅极通过二极管结构彼此连接。

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