专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07723818B2 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07723818B2
公开(公告)日：2010-05-25
申请号：US11805232
申请日：2007-05-22
申请人： Armin Tilke , Frank Huebinger , Hermann Wendt
发明人： Armin Tilke , Frank Huebinger , Hermann Wendt
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/76229 , H01L21/76232
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括工件和形成在工件内的沟槽。沟槽具有上部和下部，上部具有第一宽度，下部具有第二宽度，第二宽度大于第一宽度。第一材料至少部分地在下部的第二宽度大于上部的第一宽度的区域中设置在沟槽的下部。第二材料设置在沟槽的上部，并且至少在上部下方的沟槽的下部。

32. 发明申请

US20080290448A1 Semiconductor devices and methods of manufacture thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080290448A1
公开(公告)日：2008-11-27
申请号：US11805232
申请日：2007-05-22
申请人： Armin Tilke , Frank Huebinger , Hermann Wendt
发明人： Armin Tilke , Frank Huebinger , Hermann Wendt
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/76232
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括工件和形成在工件内的沟槽。沟槽具有上部和下部，上部具有第一宽度，下部具有第二宽度，第二宽度大于第一宽度。第一材料至少部分地在下部的第二宽度大于上部的第一宽度的区域中设置在沟槽的下部。第二材料设置在沟槽的上部，并且至少在上部下方的沟槽的下部。

33. 发明授权

US09401322B2 Semiconductor devices and structures thereof 有权
标题翻译：半导体器件及其结构
公开(公告)号：US09401322B2
公开(公告)日：2016-07-26
申请号：US13190310
申请日：2011-07-25
申请人： Markus Naujok , Hermann Wendt , Alois Gutmann , Muhammed Shafi Pallachalil
发明人： Markus Naujok , Hermann Wendt , Alois Gutmann , Muhammed Shafi Pallachalil
IPC分类号： H01L29/40 , H01L23/522 , H01L21/768
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.
摘要翻译：公开了一种在互连之间具有气隙的结构。第一绝缘材料沉积在工件上，并且具有牺牲部分的第二绝缘材料沉积在第一绝缘材料上。导电线形成在第一和第二绝缘层中。处理第二绝缘材料以去除牺牲部分，并且去除第一绝缘材料的至少一部分，在导线之间形成气隙。第二绝缘材料在处理它以去除牺牲部分之后是不可渗透的并且是可渗透的。工件的第一区域可以在处理期间被掩蔽，使得第二绝缘材料在工件的第二区域变得可渗透，但在第一区域中仍然不可渗透，从而允许在第二区域中形成气隙，但是不是第一个地区。

34. 发明申请

US20120025382A1 Devices Formed With Dual Damascene Process 有权
标题翻译：形成双镶嵌工艺的装置
公开(公告)号：US20120025382A1
公开(公告)日：2012-02-02
申请号：US13271878
申请日：2011-10-12
申请人： Philipp Riess , Erdem Kaltalioglu , Hermann Wendt
发明人： Philipp Riess , Erdem Kaltalioglu , Hermann Wendt
IPC分类号： H01L23/532 , H01L23/528
CPC分类号： H01L23/53238 , H01L21/31608 , H01L21/31629 , H01L21/31695 , H01L21/76808 , H01L21/76816 , H01L23/5226 , H01L23/53228 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.
摘要翻译：公开了在半导体部件上形成金属化层的结构和方法。该方法包括使用金属线掩模蚀刻金属线沟槽，并且在蚀刻金属线沟槽之后使用通孔掩模蚀刻通孔沟槽。通孔沟槽仅在金属线掩模和通孔掩模两者共同的区域中被蚀刻。

35. 发明申请

US20110278730A1 Semiconductor Devices and Structures Thereof 审中-公开
标题翻译：半导体器件及其结构
公开(公告)号：US20110278730A1
公开(公告)日：2011-11-17
申请号：US13190310
申请日：2011-07-25
申请人： Markus Naujok , Hermann Wendt , Alois Gutmann
发明人： Markus Naujok , Hermann Wendt , Alois Gutmann
IPC分类号： H01L23/48 , B82Y99/00
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.
摘要翻译：公开了一种在互连之间具有气隙的结构。第一绝缘材料沉积在工件上，并且具有牺牲部分的第二绝缘材料沉积在第一绝缘材料上。导电线形成在第一和第二绝缘层中。处理第二绝缘材料以去除牺牲部分，并且去除第一绝缘材料的至少一部分，在导线之间形成气隙。第二绝缘材料在处理它以去除牺牲部分之后是不可渗透的并且是可渗透的。工件的第一区域可以在处理期间被掩蔽，使得第二绝缘材料在工件的第二区域变得可渗透，但在第一区域中仍然不可渗透，从而允许在第二区域中形成气隙，但是不是第一个地区。

36. 发明授权

US07906426B2 Method of controlled low-k via etch for Cu interconnections 有权
标题翻译：用于Cu互连的受控低k通孔蚀刻的方法
公开(公告)号：US07906426B2
公开(公告)日：2011-03-15
申请号：US11788969
申请日：2007-04-23
申请人： Wuping Liu , Johnny Widodo , Teck Jung Tang , Jing Hui Li , Han Wah Ng , Larry A. Clevenger , Hermann Wendt
发明人： Wuping Liu , Johnny Widodo , Teck Jung Tang , Jing Hui Li , Han Wah Ng , Larry A. Clevenger , Hermann Wendt
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/31111 , H01L21/31116 , H01L21/31138
摘要： An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.
摘要翻译：互连堆叠及其制造方法，其中互连具有垂直侧壁通孔。互连堆叠包括衬底，形成在衬底中的金属互连，形成在衬底上的蚀刻阻挡层和金属互连，以及层间电介质（ILD）层，其具有形成在其中的至少一个通孔，其延伸穿过形成在衬底上的过渡层蚀刻停止层。通过将ILD蚀刻到第一深度并且使互连堆叠灰化以修改通过蚀刻形成的通路的部分与过渡层之间的ILD的一部分而形成通孔。灰化将ILD的这部分转化为氧化物材料。该方法包括湿蚀刻互连以去除氧化物材料和过渡层的一部分，以形成延伸穿过ILD到蚀刻停止层的通孔。

37. 发明申请

US20100197112A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100197112A1
公开(公告)日：2010-08-05
申请号：US12762172
申请日：2010-04-16
申请人： Armin Tilke , Frank Huebinger , Hermann Wendt
发明人： Armin Tilke , Frank Huebinger , Hermann Wendt
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/76232
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括工件和形成在工件内的沟槽。沟槽具有上部和下部，上部具有第一宽度，下部具有第二宽度，第二宽度大于第一宽度。第一材料至少部分地在下部的第二宽度大于上部的第一宽度的区域中设置在沟槽的下部。第二材料设置在沟槽的上部，并且至少在上部下方的沟槽的下部。

38. 发明申请

US20100032841A1 Semiconductor Devices and Structures Thereof 有权
标题翻译：半导体器件及其结构
公开(公告)号：US20100032841A1
公开(公告)日：2010-02-11
申请号：US12579807
申请日：2009-10-15
申请人： Markus Naujok , Hermann Wendt , Alois Gutmann , Muhammed Shafi Pallachalil
发明人： Markus Naujok , Hermann Wendt , Alois Gutmann , Muhammed Shafi Pallachalil
IPC分类号： H01L23/522
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.
摘要翻译：公开了一种在互连之间具有气隙的结构。第一绝缘材料沉积在工件上，并且具有牺牲部分的第二绝缘材料沉积在第一绝缘材料上。导电线形成在第一和第二绝缘层中。处理第二绝缘材料以去除牺牲部分，并且去除第一绝缘材料的至少一部分，在导线之间形成气隙。第二绝缘材料在处理它以去除牺牲部分之后是不可渗透的并且是可渗透的。工件的第一区域可以在处理期间被掩蔽，使得第二绝缘材料在工件的第二区域变得可渗透，但在第一区域中仍然不可渗透，从而允许在第二区域中形成气隙，但是不是第一个地区。

39. 发明授权

US07452804B2 Single damascene with disposable stencil and method therefore 有权
标题翻译：具有一次性模板的单镶嵌和方法
公开(公告)号：US07452804B2
公开(公告)日：2008-11-18
申请号：US11204982
申请日：2005-08-16
申请人： Michael Beck , Bee Kim Hong , Armin Tilke , Hermann Wendt
发明人： Michael Beck , Bee Kim Hong , Armin Tilke , Hermann Wendt
IPC分类号： H01L21/00
CPC分类号： H01L21/76885 , Y10S438/926
摘要： In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited over exposed surfaces of the stencil pattern, and the exposed horizontal surfaces of the second liner are removed by sputtering. A low-k dielectric layer is then deposited over the wafer, and the wafer is planarized down to the stencil pattern by chemical-mechanical polishing. The stencil pattern is removed with a wet etch to form an aperture in the wafer exposing the liner and remaining portions of the second liner. Metal is deposited in the aperture, and the surface of the wafer is replanarized by chemical-mechanical polishing to produce a planar surface for additional metallization layers that may be deposited.
摘要翻译：在制造半导体器件的方法中，衬垫沉积在晶片的导电区域上，并且模板层沉积在衬垫上。蚀刻模板层和衬垫以形成用于导电层的模板图案。第二衬里沉积在模板图案的暴露表面上，并且通过溅射去除第二衬里的暴露的水平表面。然后将低k电介质层沉积在晶片上，并且通过化学机械抛光将晶片平面化到模板图案。用湿蚀刻去除模板图案，以在晶片中形成暴露衬垫和第二衬垫的剩余部分的孔。金属沉积在孔中，晶片的表面通过化学机械抛光进行再生，以产生可沉积的附加金属化层的平面。

40. 发明申请

US20080108219A1 Semiconductor interconnect and method of making same 有权
标题翻译：半导体互连及其制作方法
公开(公告)号：US20080108219A1
公开(公告)日：2008-05-08
申请号：US11592427
申请日：2006-11-03
申请人： Frank Huebinger , Moosung Chae , Armin Tilke , Hermann Wendt
发明人： Frank Huebinger , Moosung Chae , Armin Tilke , Hermann Wendt
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L21/7684 , H01L21/76849 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit interconnect structure includes a conductive line, a first barrier layer disposed on a bottom surface of conductive line, a second barrier layer disposed on the top surface of the conductive line, and an interlevel dielectric surrounding the conductive line.
摘要翻译：集成电路互连结构包括导线，布置在导线底面上的第一阻挡层，设置在导线上表面的第二阻挡层和围绕导线的层间电介质。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式