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31. 发明申请

US20140061658A1 High Electron Mobility Transistor and Manufacturing Method Thereof 审中-公开
标题翻译：高电子迁移率晶体管及其制造方法
公开(公告)号：US20140061658A1
公开(公告)日：2014-03-06
申请号：US13603392
申请日：2012-09-04
申请人： Chien-Wei Chiu , Tsung-Yi Huang
发明人： Chien-Wei Chiu , Tsung-Yi Huang
IPC分类号： H01L29/778 , H01L21/338
CPC分类号： H01L29/1033 , H01L21/76224 , H01L29/1029 , H01L29/2003 , H01L29/42364 , H01L29/66462 , H01L29/7787
摘要： The present invention discloses an enhanced mode high electron mobility transistor (HEMT) which includes: a P-type gallium nitride (GaN) layer; a barrier layer, which is formed on and connected to the GaN layer; a dielectric layer, which is formed on and connected to the GaN layer, wherein the barrier layer does not overlap at least part of the dielectric layer; a gate, which is formed on the dielectric layer for receiving a gate voltage; and a source and a drain, which are formed at two sides of the gate on the GaN layer respectively; wherein a two dimensional electron gas (2DEG) is formed at a junction of the GaN layer and the barrier layer which does not include a portion of the junction below the gate, and the 2DEG does not electrically connect the source to the drain when there is no voltage applied to the gate.
摘要翻译：本发明公开了一种增强型高电子迁移率晶体管（HEMT），其包括：P型氮化镓（GaN）层; 阻挡层，其形成在GaN层上并连接到GaN层; 形成在GaN层上并连接到GaN层的电介质层，其中阻挡层不与电介质层的至少一部分重叠; 栅极，其形成在用于接收栅极电压的电介质层上; 以及源极和漏极，其分别形成在GaN层上的栅极的两侧; 其中在GaN层和阻挡层的结合处形成二维电子气（2DEG），其不包括在栅极下方的结的一部分，并且当存在时，2DEG不将源电连接到漏极没有电压施加到门。

32. 发明授权

US08575693B1 Double diffused metal oxide semiconductor device 有权
标题翻译：双扩散金属氧化物半导体器件
公开(公告)号：US08575693B1
公开(公告)日：2013-11-05
申请号：US13480360
申请日：2012-05-24
申请人： Tsung-Yi Huang , Chien-Wei Chiu , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Wei Chiu , Chien-Hao Huang
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/66681
摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device. The DMOS device is formed in a substrate, and includes a high voltage well, a first field oxide region, a first gate, a first source, a drain, a body region, a body electrode, a second field oxide region, a second gate, and a second source. The second field oxide region and the first field oxide region are separated by the high voltage well and the body region. A part of the second gate is on the second field oxide region, and another part of the second gate is on the body region. The second gate is electrically connected to the first gate, and the second source is electrically connected to the first source, such that when the DMOS device is ON, a surface channel and a buried channel are formed.
摘要翻译：本发明公开了一种双扩散金属氧化物半导体（DMOS）装置。 DMOS器件形成在衬底中，并且包括高电压阱，第一场氧化物区域，第一栅极，第一源极，漏极，体区域，体电极，第二场氧化物区域，第二栅极，和第二个来源。第二场氧化物区域和第一场氧化物区域被高电压井和身体区域分开。第二栅极的一部分在第二场氧化物区域上，第二栅极的另一部分位于主体区域上。第二栅极电连接到第一栅极，并且第二源极电连接到第一源极，使得当DMOS器件导通时，形成表面沟道和埋入沟道。

33. 发明申请

US20130270634A1 HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：高压器件及其制造方法
公开(公告)号：US20130270634A1
公开(公告)日：2013-10-17
申请号：US13445151
申请日：2012-04-12
申请人： Tsung-Yi Huang , Chien-Wei Chiu
发明人： Tsung-Yi Huang , Chien-Wei Chiu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/823412 , H01L21/823418 , H01L27/088 , H01L29/1045 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate. A low voltage device is also formed in the substrate. The high voltage device includes a drift region, a gate, a source, a drain, and a mitigation region. The mitigation region has a second conductive type, and is formed in the drift region between the gate and drain. The mitigation region is formed by a process step which also forms a lightly doped drain (LDD) region in the low voltage device.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压器件形成在第一导电型衬底中。在基板中也形成低压器件。高电压装置包括漂移区域，栅极，源极，漏极和缓解区域。缓解区域具有第二导电类型，并且形成在栅极和漏极之间的漂移区域中。缓解区域由在低电压装置中也形成轻掺杂漏极（LDD）区的工艺步骤形成。

34. 发明申请

US20130181253A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130181253A1
公开(公告)日：2013-07-18
申请号：US13353053
申请日：2012-01-18
申请人： Tsung-Yi Huang , Chien-Wei Chiu , Chien-Hao Huang
发明人： Tsung-Yi Huang , Chien-Wei Chiu , Chien-Hao Huang
IPC分类号： H01L29/72 , H01L21/331
CPC分类号： H01L29/7396 , H01L29/0611 , H01L29/0619 , H01L29/0623
摘要： The present invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure is formed in a first conductive type substrate, which has an upper surface. The semiconductor structure includes: a protected device, at least a buried trench, and at least a doped region. The protected device is formed in the substrate. The buried trench is formed below the upper surface with a first depth, and the buried trench surrounds the protected device from top view. The doped region is formed below the upper surface with a second depth, and the doped region surrounds the buried trench from top view. The second depth is not less than the first depth.
摘要翻译：本发明公开了一种半导体结构及其制造方法。半导体结构形成在具有上表面的第一导电型基板中。半导体结构包括：受保护器件，至少埋入沟槽和至少掺杂区域。受保护的器件形成在衬底中。埋设的沟槽形成在上表面下方具有第一深度，并且埋入的沟槽从顶视图围绕受保护的器件。掺杂区域形成在具有第二深度的上表面下方，并且掺杂区域从顶视图围绕埋入沟槽。第二深度不小于第一深度。

35. 发明申请

US20120193707A1 High voltage multigate device and manufacturing method thereof 审中-公开
标题翻译：高压多器件及其制造方法
公开(公告)号：US20120193707A1
公开(公告)日：2012-08-02
申请号：US13065569
申请日：2011-03-24
申请人： Tsung-Yi Huang , Chien-Wei Chiu
发明人： Tsung-Yi Huang , Chien-Wei Chiu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/0657 , H01L29/42356 , H01L29/42392 , H01L29/66704 , H01L29/7824 , H01L29/7827 , H01L29/7831 , H01L29/7833 , H01L29/7835 , H01L29/785 , H01L29/7855 , H01L29/78696
摘要： The present invention discloses a high voltage multigate device and a manufacturing method thereof. The high voltage multigate device includes: a semiconductor fin doped with first conductive type impurities; a dielectric layer, which overlays a portion of the semiconductor fin; a gate which overlays the dielectric layer; a drain doped with second conductive type impurities, which is formed in the semiconductor fin or coupled to the semiconductor fin; a source doped with second conductive type impurities, which is formed in the semiconductor fin or coupled to the semiconductor fin, wherein the drain and the source are located at different sides of the gate; and a drift region or a well doped with second conductive type impurities, which is formed in the semiconductor fin at least between the drain and the gate.
摘要翻译：本发明公开了一种高压多电位装置及其制造方法。高电压多器件包括：掺杂有第一导电类型杂质的半导体鳍片; 介电层，覆盖半导体鳍片的一部分; 覆盖介电层的栅极; 掺杂有第二导电类型杂质的漏极，其形成在半导体鳍片中或耦合到半导体鳍片; 掺杂有第二导电类型杂质的源，其形成在半导体鳍片中或耦合到半导体鳍片，其中漏极和源极位于栅极的不同侧; 以及漂移区或掺杂有第二导电类型杂质的阱，其至少在漏极和栅极之间形成在半导体鳍片中。

36. 发明授权

US08400177B2 Device and method for testing display panel 有权
标题翻译：显示面板测试装置及方法
公开(公告)号：US08400177B2
公开(公告)日：2013-03-19
申请号：US12551204
申请日：2009-08-31
申请人： Chien-Wei Chiu , An-Ting Hsiao
发明人： Chien-Wei Chiu , An-Ting Hsiao
IPC分类号： G01R31/26 , G01R31/02 , H01R3/00
CPC分类号： G01R1/0416 , G09G3/006 , H05K1/0268 , H05K3/365
摘要： A testing device is provided for testing a display panel including a first circuit board. The testing device includes a second circuit board and a pressing element. The second circuit board includes a main body, multiple test pads, multiple testing circuits and multiple conducting elements. The test pads are arranged on a first surface of the main body and corresponding to respective pins of the first circuit board. The testing circuits are formed on the second surface of the main body and corresponding to respective test pads. The first circuit board is stacked on the second circuit board. The testing circuits are electrically with respective pins through respective conducting elements and respective test pads. The pressing element presses a stacking region between the first circuit board and the second circuit board, thereby facilitating close contact between the first circuit board and the second circuit board.
摘要翻译：提供了一种用于测试包括第一电路板的显示面板的测试装置。测试装置包括第二电路板和按压元件。第二电路板包括主体，多个测试焊盘，多个测试电路和多个导电元件。测试垫布置在主体的第一表面上并且对应于第一电路板的相应引脚。测试电路形成在主体的第二表面上并且对应于相应的测试焊盘。第一电路板堆叠在第二电路板上。测试电路通过相应的导电元件和相应的测试焊盘与相应的引脚电连接。按压元件按压第一电路板和第二电路板之间的堆叠区域，从而促进第一电路板和第二电路板之间的紧密接触。

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