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31. 发明授权

US6091121A Semiconductor device and method for manufacturing the same 失效
公开(公告)号：US6091121A
公开(公告)日：2000-07-18
申请号：US190826
申请日：1998-11-12
申请人： Noriaki Oda
发明人： Noriaki Oda
IPC分类号： H01L21/336 , H01L21/314 , H01L21/316 , H01L21/318 , H01L23/00 , H01L29/78
CPC分类号： H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/3145 , H01L21/31612 , H01L21/31625 , H01L21/3185 , H01L23/564 , H01L2924/0002 , H01L2924/13091 , Y10S257/90
摘要： In an LDD structure MOSFET, a protecting multilayer insulating film is formed to cover a gate electrode in order to protect the gate electrode and the gate oxide film from a moisture included in an upper level layer. The protecting multilayer insulating film includes a protecting nitride film for preventing infiltration of moisture, and another protecting insulator film having a compressive stress for relaxing a tensile stress of the protecting nitride film. Thus, it is possible to prevent infiltration of moisture, and simultaneously, it is possible to minimize energy levels for trapping electrons and holes, which would have otherwise been formed within the gate oxide film and at a boundary between the gate oxide film and the semiconductor substrate because of the tensile stress of the protecting nitride film.

32. 发明授权

US06060784A Interconnection layer structure in a semiconductor integrated circuit device having macro cell regions 失效
标题翻译：具有宏单元区域的半导体集成电路器件中的互连层结构
公开(公告)号：US06060784A
公开(公告)日：2000-05-09
申请号：US768577
申请日：1996-12-18
申请人： Noriaki Oda
发明人： Noriaki Oda
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/528 , H01L23/532 , H01L27/118 , H01L23/48 , H01L29/12
CPC分类号： H01L23/5283 , H01L23/53223 , H01L27/11803 , H01L2924/0002 , Y10S257/915
摘要： An interconnection layer extends across at least a macro cell region and at least a circuit region other than the macro cell region, the macro cell region and the circuit region being monolithically integrated into a semiconductor device, wherein the interconnection layer in the macro cell region is thinner than the interconnection layer in the circuit region.
摘要翻译：互连层至少延伸到宏小区区域和至少一个宏小区区域以外的电路区域，宏小区区域和电路区域被单片地集成到半导体器件中，其中宏小区区域中的互连层是比电路区域中的互连层薄。

33. 发明授权

US5990001A Method of forming a semiconductor device having a critical path wiring 失效
标题翻译：形成具有关键路径布线的半导体器件的方法
公开(公告)号：US5990001A
公开(公告)日：1999-11-23
申请号：US977659
申请日：1997-11-24
申请人： Noriaki Oda
发明人： Noriaki Oda
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/528 , H01L23/532 , H01L21/283
CPC分类号： H01L23/5222 , H01L23/5283 , H01L23/53223 , H01L2924/0002
摘要： Disclosed is a semiconductor device, which has: a wiring corresponding to a critical path, a wiring delay time of which determines an operating speed of an entire circuit, and a wiring corresponding to other than the critical path. The critical path wiring and the other wiring are formed on the same wiring layer, wherein a thickness of at least a part of the critical path wiring is greater than that of the other wiring.
摘要翻译：公开了一种半导体器件，其具有：对应于关键路径的布线，其布线延迟时间决定整个电路的操作速度，以及对应于关键路径以外的布线。关键路径布线和其他布线形成在相同布线层上，其中至少一部分关键路径布线的厚度大于其它布线的厚度。

34. 发明授权

US5479053A Semiconductor device with conductor clad insulator wiring 失效
标题翻译：具有导体包覆绝缘体布线的半导体器件
公开(公告)号：US5479053A
公开(公告)日：1995-12-26
申请号：US65629
申请日：1993-05-21
申请人： Noriaki Oda
发明人： Noriaki Oda
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/66 , H01L23/48
CPC分类号： H01L23/66 , H01L23/5283 , H01L23/53242 , H01L23/53247 , H01L2924/0002
摘要： A semiconductor device which comprises a first insulator, a first conductor disposed on one side near a semiconductor substrate, a second conductor disposed on the opposite side to the substrate forming a tubular member together with the first conductor, and a second insulator surrounding the member. The first insulator is incorporated into the member, and the member and the first insulator constitute an electrical wiring. Since the wiring is composed of the first insulator and the first and second conductors surrounding the first insulator, an electric current flows through the tubular member of the conductors. Therefore, when the device is operated by a high-frequency (for example 80 GHz or more) electric current, apparent increase of the wiring resistance due to the "skin effect" hardly occurs and as a result, reduction of the operating speed can be prevented.
摘要翻译：一种半导体器件，包括第一绝缘体，设置在靠近半导体衬底的一侧的第一导体，设置在与衬底相反的一侧的第二导体，与第一导体一起形成管状构件，以及围绕该构件的第二绝缘体。第一绝缘体被结合到构件中，并且构件和第一绝缘体构成电气布线。由于布线由第一绝缘体和围绕第一绝缘体的第一和第二导体组成，所以电流流过导体的管状构件。因此，当器件通过高频（例如80GHz以上）的电流进行工作时，几乎不发生由于“皮肤效应”导致的布线电阻的明显增加，结果，可以降低工作速度防止了

35. 发明授权

US08330276B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08330276B2
公开(公告)日：2012-12-11
申请号：US12837069
申请日：2010-07-15
申请人： Noriaki Oda , Shinichi Chikaki
发明人： Noriaki Oda , Shinichi Chikaki
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/53295 , H01L21/76808 , H01L21/7682 , H01L21/76825 , H01L21/76828 , H01L21/76835 , H01L23/53238 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes a first interconnect layer insulating film, first copper interconnects that are embedded in the first interconnect layer insulating film, and an interlayer insulating film that is formed on the first copper interconnects and the first interconnect layer insulating film. The semiconductor device includes a second interconnect layer insulating film that is formed on the interlayer insulating film and second copper interconnects that are embedded in the second interconnect layer insulating film. The first and second interconnect layer insulating films include first and second low dielectric constant films, respectively. The interlayer insulating film has higher mechanical strength than the first and second interconnect layer insulating films.
摘要翻译：半导体器件包括第一互连层绝缘膜，嵌入在第一互连层绝缘膜中的第一铜互连以及形成在第一铜互连和第一互连层绝缘膜上的层间绝缘膜。半导体器件包括形成在层间绝缘膜上的第二互连层绝缘膜和嵌入第二互连层绝缘膜中的第二铜互连。第一和第二互连层绝缘膜分别包括第一和第二低介电常数膜。层间绝缘膜具有比第一和第二互连层绝缘膜更高的机械强度。

36. 发明授权

US07763968B2 Semiconductor device featuring large reinforcing elements in pad area 有权
标题翻译：半导体器件在焊盘区域具有大的增强元件
公开(公告)号：US07763968B2
公开(公告)日：2010-07-27
申请号：US11526572
申请日：2006-09-26
申请人： Hiroyuki Kunishima , Noriaki Oda
发明人： Hiroyuki Kunishima , Noriaki Oda
IPC分类号： H01L23/12 , H01L21/4763
CPC分类号： H01L24/05 , H01L23/528 , H01L2224/05093 , H01L2224/05624 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/13091 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor device, a plurality of interconnections are formed in an interconnection formation insulating interlayer, and a plurality of reinforcing elements are substantially evenly formed in blank areas of the interconnection insulating interlayer in which no interconnection is formed. A wire-bonding electrode pad is provided above the interconnection formation insulating interlayer so that a pad area, on which the wire-bonding electrode pad is projected, is defined on the interconnection formation insulating interlayer. A part of the reinforcing elements included in the pad area features a larger size than that of the remaining reinforcing elements.
摘要翻译：在半导体器件中，在互连形成绝缘中间层中形成多个互连，并且在互连绝缘中间层的不形成互连的空白区域中大致均匀地形成多个增强元件。在互连形成绝缘中间层上方设置引线接合电极焊盘，使得在互连形成绝缘中间层上限定引线接合电极焊盘的焊盘区域。包括在垫区域中的增强元件的一部分具有比剩余的增强元件的尺寸更大的尺寸。

37. 发明申请

US20070069388A1 Semiconductor device featuring large reinforcing elements in pad area, and pattern design apparatus therefor 有权
标题翻译：在垫区域中具有大的增强元件的半导体器件及其图案设计装置
公开(公告)号：US20070069388A1
公开(公告)日：2007-03-29
申请号：US11526572
申请日：2006-09-26
申请人： Hiroyuki Kunishima , Noriaki Oda
发明人： Hiroyuki Kunishima , Noriaki Oda
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/528 , H01L2224/05093 , H01L2224/05624 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/13091 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor device, a plurality of interconnections are formed in an interconnection formation insulating interlayer, and a plurality of reinforcing elements are substantially evenly formed in blank areas of the interconnection insulating interlayer in which no interconnection is formed. A wire-bonding electrode pad is provided above the interconnection formation insulating interlayer so that a pad area, on which the wire-bonding electrode pad is projected, is defined on the interconnection formation insulating interlayer. A part of the reinforcing elements included in the pad area features a larger size than that of the remaining reinforcing elements.
摘要翻译：在半导体器件中，在互连形成绝缘中间层中形成多个互连，并且在互连绝缘中间层的不形成互连的空白区域中大致均匀地形成多个增强元件。在互连形成绝缘中间层上方设置引线接合电极焊盘，使得在互连形成绝缘中间层上限定引线接合电极焊盘的焊盘区域。包括在垫区域中的增强元件的一部分具有比剩余的增强元件的尺寸更大的尺寸。

38. 发明申请

US20060276029A1 Semiconductor device and method for manufacturing same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060276029A1
公开(公告)日：2006-12-07
申请号：US11503972
申请日：2006-08-15
申请人： Tatsuya Usami , Takashi Ishigami , Tetsuya Kurokawa , Noriaki Oda
发明人： Tatsuya Usami , Takashi Ishigami , Tetsuya Kurokawa , Noriaki Oda
IPC分类号： H01L21/4763
CPC分类号： H01L23/53295 , H01L21/76829 , H01L21/76832 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu film 209 is formed in multilayer films comprising a L-Ox™ film 203 and a SiO2 film 204. Since the L-Ox™ film 203 comprises ladder-shaped siloxane hydride structure, the film thickness and the film characteristics are stable, and thus changes in the film quality is scarcely occurred during the manufacturing process.
摘要翻译：本发明降低了层间绝缘膜的有效介电常数，同时抑制了由吸湿引起的半导体器件的可靠性的降低。包括Cu膜209的铜互连形成在包括L-Ox TM膜203和SiO 2膜204的多层膜中。由于L-Ox TM膜203包括梯形 - 形成硅氧烷氢化物结构，膜厚度和膜特性是稳定的，因此在制造过程中几乎不发生膜质量的变化。

39. 发明授权

US06358802B1 Method for manufacturing semiconductor device having a gate electrode film containing nitrogen 失效
标题翻译：具有含有氮的栅极电极的半导体器件的制造方法
公开(公告)号：US06358802B1
公开(公告)日：2002-03-19
申请号：US09298699
申请日：1999-04-23
申请人： Noriaki Oda
发明人： Noriaki Oda
IPC分类号： H01L21336
CPC分类号： H01L29/518 , H01L21/28176 , H01L21/76832 , H01L21/76834 , H01L23/3171 , H01L29/4983 , H01L2924/0002 , H01L2924/00
摘要： There is disclosed a semiconductor device which includes a semiconductor substrate having an element region and source and drain regions, a gate dielectric film containing nitrogen formed in the element region of said semiconductor substrate, a gate electrode formed on the gate dielectric film, a first dielectric film formed adjacent to the gate electrode so as to define a side wall therefor, a second dielectric film formed so as to cover the gate electrode and the first dielectric film, the second dielectric film being doped with nitrogen, and a third dielectric film formed so as to cover the second dielectric film, the third dielectric film being formed of silicon nitride. A method for manufacturing such a semiconductor device is also described.
摘要翻译：公开了一种半导体器件，其包括具有元件区域和源极和漏极区域的半导体衬底，包含形成在所述半导体衬底的元件区域中的氮的栅极电介质膜，形成在栅极电介质膜上的栅电极，第一电介质形成在栅电极附近以形成侧壁，形成为覆盖栅电极和第一电介质膜的第二电介质膜，第二电介质膜被掺杂氮，第三电介质膜形成为为了覆盖第二电介质膜，第三电介质膜由氮化硅形成。还描述了制造这种半导体器件的方法。

40. 发明授权

US06316833B1 Semiconductor device with multilayer interconnection having HSQ film with implanted fluorine and fluorine preventing liner 失效
标题翻译：具有多层互连的半导体器件具有带氟氟防氟衬里的HSQ膜
公开(公告)号：US06316833B1
公开(公告)日：2001-11-13
申请号：US09305425
申请日：1999-05-05
申请人： Noriaki Oda
发明人： Noriaki Oda
IPC分类号： H01L2348
CPC分类号： H01L23/5329 , H01L21/7682 , H01L21/76825 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with a multilevel interconnection has hydrogen silsesquioxane films which are made porous by etching action of hydrogen fluoride or by ion-implantation of impurities containing fluorine, as an interlayer insulating film for filling up a space between wires. Consequently, a dielectric constant of HSQ is low and wiring capacitance of the multilayer interconnection can be reduced.
摘要翻译：具有多层互连的半导体器件具有通过氟化氢的蚀刻作用或通过离子注入含氟杂质而制成多孔的氢倍半硅氧烷膜，作为用于填充电线之间的间隔的层间绝缘膜。因此，HSQ的介电常数低，可以降低多层互连的布线电容。

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