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1. 发明申请

US20110049719A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110049719A1
公开(公告)日：2011-03-03
申请号：US12837069
申请日：2010-07-15
申请人： Noriaki Oda , Shinichi Chikaki
发明人： Noriaki Oda , Shinichi Chikaki
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/76808 , H01L21/7682 , H01L21/76825 , H01L21/76828 , H01L21/76835 , H01L23/53238 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes a first interconnect layer insulating film, first copper interconnects that are embedded in the first interconnect layer insulating film, and an interlayer insulating film that is formed on the first copper interconnects and the first interconnect layer insulating film. The semiconductor device includes a second interconnect layer insulating film that is formed on the interlayer insulating film and second copper interconnects that are embedded in the second interconnect layer insulating film. The first and second interconnect layer insulating films include first and second low dielectric constant films, respectively. The interlayer insulating film has higher mechanical strength than the first and second interconnect layer insulating films.
摘要翻译：半导体器件包括第一互连层绝缘膜，嵌入在第一互连层绝缘膜中的第一铜互连以及形成在第一铜互连和第一互连层绝缘膜上的层间绝缘膜。半导体器件包括形成在层间绝缘膜上的第二互连层绝缘膜和嵌入第二互连层绝缘膜中的第二铜互连。第一和第二互连层绝缘膜分别包括第一和第二低介电常数膜。层间绝缘膜具有比第一和第二互连层绝缘膜更高的机械强度。

2. 发明申请

US20100314777A1 Semiconductor device and method for manufacturing same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100314777A1
公开(公告)日：2010-12-16
申请号：US12662772
申请日：2010-05-03
申请人： Noriaki Oda
发明人： Noriaki Oda
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76804 , H01L21/76808 , H01L21/76831 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; an interconnect (second interconnect trench) composed of a metallic film provided in an interconnect trench (second copper interconnect) and a plug composed of a metallic film provided in a connection hole (via hole) coupled to the second interconnect trench, both of which are provided in the interlayer insulating film; a first sidewall provided on a side surface of the via hole; and a second sidewall provided on a side surface of the second interconnect trench, and a thickness of the first sidewall in vicinity of a bottom of the side surface of the via hole is larger than a thickness of the second sidewall in vicinity of a bottom of the second interconnect trench.
摘要翻译：半导体器件包括：半导体衬底; 设置在所述半导体基板上的层间绝缘膜; 由设置在互连沟槽（第二铜互连）中的金属膜构成的互连（第二互连沟槽）和由设置在耦合到第二互连沟槽的连接孔（通孔）中的金属膜构成的插塞，两者均为设置在层间绝缘膜中; 设置在所述通孔的侧面上的第一侧壁; 以及设置在所述第二互连沟槽的侧表面上的第二侧壁，并且所述通孔的所述侧表面的底部附近的所述第一侧壁的厚度大于所述第二侧壁附近的所述第二侧壁的厚度，第二互连沟槽。

3. 发明申请

US20060076596A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060076596A1
公开(公告)日：2006-04-13
申请号：US11231767
申请日：2005-09-22
申请人： Hiroaki Ohkubo , Noriaki Oda , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Noriaki Oda , Yasutaka Nakashiba
IPC分类号： H01L29/94
CPC分类号： H01L28/40
摘要： A capacity element with a simple configuration exhibits excellent production reliability. A semiconductor device 100 includes a capacity element consisting of a lower electrode 102, an SiCN film 107 and an upper electrode 113. In an insulating film 101 on a semiconductor substrate is formed a groove, in which the lower electrode 102 is buried. The lower electrode 102 includes two regions, that is, a first lower electrode 103 and a second lower electrode 105, which are separated from each other via the insulating film 101.
摘要翻译：具有简单配置的容量元件具有出色的生产可靠性。半导体器件100包括由下电极102，SiCN膜107和上电极113组成的电容元件。在半导体衬底上的绝缘膜101中形成有凹下，其中埋有下电极102。下电极102包括经由绝缘膜101彼此分离的两个区域，即第一下电极103和第二下电极105。

4. 发明授权

US06756676B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06756676B2
公开(公告)日：2004-06-29
申请号：US09863737
申请日：2001-05-23
申请人： Noriaki Oda , Kiyotaka Imai
发明人： Noriaki Oda , Kiyotaka Imai
IPC分类号： H01L2348
CPC分类号： H01L21/02131 , H01L21/022 , H01L21/02274 , H01L21/02321 , H01L21/02351 , H01L21/3105 , H01L21/31629 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device having a multilayer metallization structure using SiOF film as an interlayer insulating film, with respect to the interlayer insulating film, the fluorine concentration of SiOF films (11, 16) in a wiring gap portion in the same layer wiring is set to be higher than the fluorine concentration of SiOF films (12, 17) between the upper and lower layer wirings (8, 15; 15, 20).
摘要翻译：在具有使用SiOF膜作为层间绝缘膜的多层金属化结构的半导体器件中，相对于层间绝缘膜，将同层布线的布线间隙部分中的SiOF膜（11,16）的氟浓度设定为高于上层和下层布线（8,15; 15,20）之间的SiOF膜（12,17）的氟浓度。

5. 发明授权

US06492264B2 Semiconductor device having a silicide layer with silicon-rich region and method for making the same 失效
标题翻译：具有硅富集层的硅化物层的半导体装置及其制造方法
公开(公告)号：US06492264B2
公开(公告)日：2002-12-10
申请号：US09921882
申请日：2001-08-06
申请人： Noriaki Oda
发明人： Noriaki Oda
IPC分类号： H01L214763
CPC分类号： H01L29/456 , H01L21/28518 , H01L21/823835
摘要： A semiconductor device includes a substrate; a semiconductor region formed on the substrate; and a silicide layer as a contact layer formed directly contacting the semiconductor region; wherein the silicide layer is made to be rich in silicon while including such a silicon amount that contact resistance is significantly lowered and a method for making a semiconductor device which has the steps of: forming selectively a given conductive type semiconductor region on a substrate; forming a Co—Si alloy layer on the entire surface of the semiconductor region; introducing Si into the entire surface or part of the Co—Si alloy layer; and conducting the thermal treatment of the substrate to react the introduced Si with the Co—Si alloy layer and the Ti-included layer to form a Si-rich silicide layer including such a silicon amount that contact resistance is significantly lowered.
摘要翻译：半导体器件包括衬底; 形成在所述基板上的半导体区域; 和作为与半导体区域直接接触形成的接触层的硅化物层; 其中硅化物层被制成富含硅，同时包括接触电阻显着降低的硅量，以及制造半导体器件的方法，其具有以下步骤：在衬底上选择性地形成给定的导电型半导体区域; 在半导体区域的整个表面上形成Co-Si合金层; 将Si引入Co-Si合金层的整个表面或部分; 并进行基板的热处理，使引入的Si与Co-Si合金层和含Ti层反应，形成含硅量大的富Si硅化物层，其接触电阻显着降低。

6. 发明授权

US06320264B1 Interconnect wiring with sidewalls and inter-wiring insulation composed of fluorine 失效
标题翻译：互连线与侧壁和互连绝缘由氟组成
公开(公告)号：US06320264B1
公开(公告)日：2001-11-20
申请号：US09323124
申请日：1999-06-01
申请人： Noriaki Oda
发明人： Noriaki Oda
IPC分类号： H01L2348
CPC分类号： H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a wiring in each of one or more wiring layers formed on a semiconductor substrate, and wiring sidewall layers which are formed on side edge portions of the wiring and which include fluorine-containing silicon oxide. It is possible to form an inter-wiring insulating film comprising fluorine-containing silicon oxide or Hydroxy Silsesquioxane on the outer surface of the wiring sidewall layers. Further, it is possible to form thermally diffused regions of fluorine into which fluorine is thermally diffused from the wiring sidewall layers in the inter-wiring insulating layer and near the interfaces with the wiring sidewall layers.
摘要翻译：半导体器件包括在半导体衬底上形成的一个或多个布线层中的每一个中的布线以及形成在布线的侧边缘部分并且包括含氟氧化硅的布线侧壁层。可以在布线侧壁层的外表面上形成包含含氟氧化硅或羟基倍半硅氧烷的布线间绝缘膜。此外，可以形成氟从布线绝缘层中的布线侧壁层和与布线侧壁层的界面附近热扩散的氟的热扩散区域。

7. 发明授权

US5994749A Semiconductor device having a gate electrode film containing nitrogen 失效
标题翻译：具有含有氮的栅电极膜的半导体装置
公开(公告)号：US5994749A
公开(公告)日：1999-11-30
申请号：US8941
申请日：1998-01-20
申请人： Noriaki Oda
发明人： Noriaki Oda
IPC分类号： H01L29/78 , H01L21/28 , H01L21/318 , H01L21/336 , H01L21/768 , H01L23/31 , H01L29/49 , H01L29/51 , H01L29/76 , H01L31/113
CPC分类号： H01L29/518 , H01L21/28176 , H01L21/76832 , H01L21/76834 , H01L23/3171 , H01L29/4983 , H01L2924/0002
摘要： There is disclosed a semiconductor device which includes a semiconductor substrate having an element region and source and drain regions, a gate dielectric film containing nitrogen formed in the element region of said semiconductor substrate, a gate electrode formed on the gate dielectric film, a first dielectric film formed adjacent to the gate electrode so as to define a side wall therefor, a second dielectric film formed so as to cover the gate electrode and the first dielectric film, the second dielectric film being doped with nitrogen, and a third dielectric film formed so as to cover the second dielectric film, the third dielectric film being formed of silicon nitride. A method for manufacturing such a semiconductor device is also described.
摘要翻译：公开了一种半导体器件，其包括具有元件区域和源极和漏极区域的半导体衬底，包含形成在所述半导体衬底的元件区域中的氮的栅极电介质膜，形成在栅极电介质膜上的栅电极，第一电介质形成在栅电极附近以形成侧壁，形成为覆盖栅电极和第一电介质膜的第二电介质膜，第二电介质膜被掺杂氮，第三电介质膜形成为为了覆盖第二电介质膜，第三电介质膜由氮化硅形成。还描述了制造这种半导体器件的方法。

8. 发明授权

US08146044B2 Method of designing a semiconductor device 有权
标题翻译：设计半导体器件的方法
公开(公告)号：US08146044B2
公开(公告)日：2012-03-27
申请号：US12164391
申请日：2008-06-30
申请人： Noriaki Oda
发明人： Noriaki Oda
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5036
摘要： Aiming at providing a method of designing a semiconductor device capable of producing a semiconductor device which expresses performances adapted to required performances, the present invention sets a plurality of suites of device parameters, containing parameters relevant to transistor characteristics (transistor parameters) and parameters relevant to interconnect characteristics (interconnect parameters) corresponded to the transistor characteristics, for a single CMOS generation, selecting, out of the plurality of suites, a suite matched to performances required for a semiconductor to be designed, and designing the semiconductor device.
摘要翻译：为了提供一种能够制造能够产生适应于所需性能的性能的半导体器件的半导体器件的设计方法，本发明设置了多套器件参数，其中包含与晶体管特性（晶体管参数）相关的参数和与互连特性（互连参数）对应于晶体管特性，对于单个CMOS生成，在多个套件中选择与要设计的半导体所需的性能匹配的套件以及设计半导体器件。

9. 发明申请

US20100301488A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20100301488A1
公开(公告)日：2010-12-02
申请号：US12662807
申请日：2010-05-04
申请人： Noriaki Oda , Shinichi Chikaki
发明人： Noriaki Oda , Shinichi Chikaki
IPC分类号： H01L23/522
CPC分类号： H01L23/5329 , H01L23/5226 , H01L23/53295 , H01L24/03 , H01L24/05 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05006 , H01L2224/05093 , H01L2224/05094 , H01L2224/05096 , H01L2224/05554 , H01L2224/05556 , H01L2224/05567 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/48091 , H01L2224/48463 , H01L2224/85205 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/0105 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/19041 , H01L2924/19043 , H01L2224/45099
摘要： In a semiconductor device, a lower multi-layered interconnect structure, an intermediate via-level insulating interlayer, and an upper multi-layered interconnect structure are stacked in this order in a region overlapped with a bonding pad in a plan view; upper interconnects and vias of the upper multi-layered interconnect structure are formed so as to be connected to the bonding pad in the pad placement region; the intermediate via-level insulating interlayer has no electro-conductive material layer, which connect the interconnects or vias in the upper multi-layered interconnect structure with interconnects or vias in the lower multi-layered interconnect structure, formed therein; and the ratio of area occupied by the vias in the via-level insulating interlayers contained in the lower multi-layered interconnect structure is smaller than the ratio of area occupied by the vias in the via-level insulating interlayers contained in the upper multi-layered interconnect structure.
摘要翻译：在半导体器件中，在平面图中，在与焊盘重叠的区域中，依次层叠下层多层互连结构，中间通孔级绝缘中间层和上层多层互连结构。上部多层互连结构的上部互连和过孔形成为连接到焊盘放置区域中的焊盘; 中间通孔级绝缘中间层不具有将上部多层互连结构中的互连或通孔与其中形成的下部多层互连结构中的互连或通孔连接的导电材料层; 并且包含在下层多层互连结构中的通孔级绝缘夹层中的通孔占据的面积比例小于上层多层互连结构中包含的通孔级绝缘夹层中通孔占据的面积比互连结构。

10. 发明授权

US07230337B2 Semiconductor device including ladder-shaped siloxane hydride and method for manufacturing same 有权
标题翻译：包括梯形硅氢化硅氢化物的半导体器件及其制造方法
公开(公告)号：US07230337B2
公开(公告)日：2007-06-12
申请号：US10760554
申请日：2004-01-21
申请人： Tatsuya Usami , Takashi Ishigami , Tetsuya Kurokawa , Noriaki Oda
发明人： Tatsuya Usami , Takashi Ishigami , Tetsuya Kurokawa , Noriaki Oda
IPC分类号： H01L23/48 , H01L23/29 , H01L23/28 , H01L23/52 , H01L23/532
CPC分类号： H01L23/53295 , H01L21/76829 , H01L21/76832 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu film 209 is formed in multilayer films comprising a L-Ox™ film 203 and a SiO2 film 204. Since the L-Ox™ film 203 comprises ladder-shaped siloxane hydride structure, the film thickness and the film characteristics are stable, and thus changes in the film quality is scarcely occurred during the manufacturing process.
摘要翻译：本发明降低了层间绝缘膜的有效介电常数，同时抑制了由吸湿引起的半导体器件的可靠性的降低。包括Cu膜209的铜互连形成在包括L-Ox TM膜203和SiO 2膜204的多层膜中。由于L-Ox TM膜203包括梯形硅氢化合物结构，所以膜厚度和膜特性是稳定的，因此在制造过程中几乎不发生膜质量的变化。

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